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Thu, 11 Jun 2026 06:01:54 -0700 (PDT) Date: Thu, 11 Jun 2026 13:01:43 +0000 In-Reply-To: <20260611130144.1385343-1-abarnas@google.com> Mime-Version: 1.0 References: <20260611130144.1385343-1-abarnas@google.com> X-Mailer: git-send-email 2.54.0.1136.gdb2ca164c4-goog Message-ID: <20260611130144.1385343-6-abarnas@google.com> Subject: [RFC PATCH 5/6] arm64: execmem: enable EXECMEM_ROX_CACHE on supported CPUs From: "=?UTF-8?q?Adrian=20Barna=C5=9B?=" To: linux-arm-kernel@lists.infradead.org Cc: linux-mm@kvack.org, "=?UTF-8?q?Adrian=20Barna=C5=9B?=" , Catalin Marinas , Will Deacon , Ryan Roberts , David Hildenbrand , "Mike Rapoport (Microsoft)" , Ard Biesheuvel , Christoph Lameter , Yang Shi , Brendan Jackman Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260611_060157_187746_B25ED647 X-CRM114-Status: GOOD ( 13.18 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Enable EXECMEM_ROX_CACHE support for ARM64 systems that implement the bbml2_no_abort CPU feature. Using the ROX cache brings a performance boost by reducing linear region fragmentation caused by strict memory permissions (e.g., W^X enforcement). Grouping executable code (which is read-only in the linear region alias) into PMD-sized block mappings reduces TLB pressure and page table size. This is only enabled on systems with bbml2_no_abort, as splitting these large blocks to make pages writable during module loading would otherwise risk triggering TLB Conflict Aborts. Signed-off-by: Adrian Barna=C5=9B --- arch/arm64/Kconfig | 1 + arch/arm64/mm/init.c | 22 +++++++++++++++++++++- 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig index 38dba5f7e4d2..79c347ab841e 100644 --- a/arch/arm64/Kconfig +++ b/arch/arm64/Kconfig @@ -285,6 +285,7 @@ config ARM64 select USER_STACKTRACE_SUPPORT select VDSO_GETRANDOM select VMAP_STACK + select ARCH_HAS_EXECMEM_ROX help ARM 64-bit (AArch64) Linux support. =20 diff --git a/arch/arm64/mm/init.c b/arch/arm64/mm/init.c index 71aa745e0bef..8269d7747b84 100644 --- a/arch/arm64/mm/init.c +++ b/arch/arm64/mm/init.c @@ -420,6 +420,12 @@ void execmem_fill_trapping_insns(void *ptr, size_t siz= e) =20 flush_icache_range((unsigned long)ptr, (unsigned long)ptr + size); } + +#define MODULE_TEXT_FLAG EXECMEM_ROX_CACHE +#define MODULE_TEXT_PGPROT PAGE_KERNEL_ROX +#else +#define MODULE_TEXT_FLAG (0) +#define MODULE_TEXT_PGPROT PAGE_KERNEL #endif =20 static u64 module_direct_base __ro_after_init =3D 0; @@ -511,6 +517,8 @@ struct execmem_info __init *execmem_arch_setup(void) { unsigned long fallback_start =3D 0, fallback_end =3D 0; unsigned long start =3D 0, end =3D 0; + enum execmem_range_flags module_text_flags =3D 0; + pgprot_t module_text_pgprot =3D PAGE_KERNEL; =20 module_init_limits(); =20 @@ -531,12 +539,24 @@ struct execmem_info __init *execmem_arch_setup(void) end =3D module_plt_base + SZ_2G; } =20 + /* + * The ROX Cache requires bbml2_no_abort because it uses large block + * mappings. On systems without this guarantee, splitting these blocks + * to make pages writable for module loading can trigger TLB Conflict + * Aborts. + */ + if (system_supports_bbml2_noabort()) { + module_text_flags =3D MODULE_TEXT_FLAG; + module_text_pgprot =3D MODULE_TEXT_PGPROT; + } + execmem_info =3D (struct execmem_info){ .ranges =3D { [EXECMEM_MODULE_TEXT] =3D { .start =3D start, .end =3D end, - .pgprot =3D PAGE_KERNEL, + .flags =3D module_text_flags, + .pgprot =3D module_text_pgprot, .alignment =3D 1, .fallback_start =3D fallback_start, .fallback_end =3D fallback_end, --=20 2.54.0.1136.gdb2ca164c4-goog