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Add a 'max_clk_khz' member to the fsl_ldb_devdata structure in order to be able to set different max frequencies for other platforms. Signed-off-by: Laurentiu Palcu --- drivers/gpu/drm/bridge/fsl-ldb.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/bridge/fsl-ldb.c b/drivers/gpu/drm/bridge/fsl-ldb.c index bd03c36ee696c..b4959f654f2ac 100644 --- a/drivers/gpu/drm/bridge/fsl-ldb.c +++ b/drivers/gpu/drm/bridge/fsl-ldb.c @@ -57,6 +57,7 @@ enum fsl_ldb_devtype { IMX6SX_LDB, IMX8MP_LDB, IMX93_LDB, + IMX94_LDB, }; struct fsl_ldb_devdata { @@ -64,21 +65,31 @@ struct fsl_ldb_devdata { u32 lvds_ctrl; bool lvds_en_bit; bool single_ctrl_reg; + u32 max_clk_khz; }; static const struct fsl_ldb_devdata fsl_ldb_devdata[] = { [IMX6SX_LDB] = { .ldb_ctrl = 0x18, .single_ctrl_reg = true, + .max_clk_khz = 80000, }, [IMX8MP_LDB] = { .ldb_ctrl = 0x5c, .lvds_ctrl = 0x128, + .max_clk_khz = 80000, }, [IMX93_LDB] = { .ldb_ctrl = 0x20, .lvds_ctrl = 0x24, .lvds_en_bit = true, + .max_clk_khz = 80000, + }, + [IMX94_LDB] = { + .ldb_ctrl = 0x04, + .lvds_ctrl = 0x08, + .lvds_en_bit = true, + .max_clk_khz = 148500, }, }; @@ -274,7 +285,7 @@ fsl_ldb_mode_valid(struct drm_bridge *bridge, { struct fsl_ldb *fsl_ldb = to_fsl_ldb(bridge); - if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 160000 : 80000)) + if (mode->clock > (fsl_ldb_is_dual(fsl_ldb) ? 2 : 1) * fsl_ldb->devdata->max_clk_khz) return MODE_CLOCK_HIGH; return MODE_OK; @@ -386,6 +397,8 @@ static const struct of_device_id fsl_ldb_match[] = { .data = &fsl_ldb_devdata[IMX8MP_LDB], }, { .compatible = "fsl,imx93-ldb", .data = &fsl_ldb_devdata[IMX93_LDB], }, + { .compatible = "fsl,imx94-ldb", + .data = &fsl_ldb_devdata[IMX94_LDB], }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, fsl_ldb_match); -- 2.51.0