From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E819DCD98CE for ; Fri, 12 Jun 2026 19:29:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:Cc:To:From: Subject:Message-ID:References:Mime-Version:In-Reply-To:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=JOP4oEaU0YzeukjVbsQ2eL5dXi7XZrwslM0o9h4B8J4=; b=Xm8QwCxBRfMhkc8X9+r9RF1lzc 9+0LepiO0MuW+o6PQ0ey2sfnW/NF5+oesKUkKVDMB4/a7NycBmzdcP4b+SkqpmF/gc5bUuc+kevJk RLObXhjutX8XNBER+nsUckQ1Ur1fMhO8/iM4nBiRWcErqydbzWP8opae3UVYycw1aB0kTOj26Vcw3 mwMx4sh0L6ZSiUExh/ydZJ77+tbg3UVVCYvZlHgIAPIb+AA7Bm3/7U94NkPojW5/8ORxP4J8mODM2 rlsw7KSBSk5dBunR5V7Sp+zkG9XBISAYrCiKi9iXt1ThKzdtsM0o8mA+WcVIlESdaNgat1m8UbMoV pwCO+btw==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wY7Z8-0000000BSMA-2U5J; Fri, 12 Jun 2026 19:29:18 +0000 Received: from mail-ot1-x34a.google.com ([2607:f8b0:4864:20::34a]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wY7Z4-0000000BSJS-0Q2L for linux-arm-kernel@lists.infradead.org; Fri, 12 Jun 2026 19:29:15 +0000 Received: by mail-ot1-x34a.google.com with SMTP id 46e09a7af769-7e70409ec05so4130751a34.1 for ; Fri, 12 Jun 2026 12:29:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1781292552; x=1781897352; darn=lists.infradead.org; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:from:to:cc:subject:date:message-id:reply-to; bh=JOP4oEaU0YzeukjVbsQ2eL5dXi7XZrwslM0o9h4B8J4=; b=ZXLH19SNi1jHSRlS2WvS/K6P2E+ddHbAM1Flf1u/Ag/giaon2k1VL/uMS8dss9mIcf nh7d5pX5ECveGZJ/Bm4f1Zag3e1mTBOGCDF+y2gR01LOtx5Y+/0VBvgrSJQZcLpOL0gw FY0z4RNJppcZWQUIol4T4bP85vPcaqob9UcyWMj3tq1Rz317edM5kPTDVbWBOOjBxwL8 38DxJpxTuKe3q94StozK+qjrrJXwOj4se41E8EcB1DPCuQnGWBebkmflEllTH0nkYU41 ZyeAO6jyk91b+ctYgQIsTdCZ4s0tia7umqHgT8vdnaRy1IHYTjVTai9C4rIBootBBdHb 37qg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1781292552; x=1781897352; h=cc:to:from:subject:message-id:references:mime-version:in-reply-to :date:x-gm-message-state:from:to:cc:subject:date:message-id:reply-to; bh=JOP4oEaU0YzeukjVbsQ2eL5dXi7XZrwslM0o9h4B8J4=; b=cBfQQm9SahEMZtfGpX/WA8sMwMlzZIXiyEmNHur0rcQiSOF4pmhz6YPQdwBHS7/jR/ aRrPhCIgbD9mzbcR5Uv9rTUsKPEj6j0++5DPGC4UX+pIEvCr8pJd6LWm+YBYGSiwIlvY RkUwvawlJoGmUwH38pqJ1xLiguxvxfJ0ywMlBc2CgqO8KgR79vEXdlKHvcMfOwpQf7Ge RAHbVP610C5LRSg0ZKmmzO2lmg+5Qvpqi3btnmFJi8yQeJXBA8i8OcM3jlKf/cJGvU6n /1OI5lSUBtG0qo5EaWOaFxv5M1D9qkr+7sDnAySK8fmmiV7nz7euVsnTz4urytJC4zGV X/jg== X-Forwarded-Encrypted: i=1; AFNElJ88oa4qD2pahunrUaJg7B48rA/NhmNBbNX9thvYPNDIp1nPjNpz2RgKwlngQz8kcdDC6ITg2n0U8lV04D97RXLU@lists.infradead.org X-Gm-Message-State: AOJu0Yx5Bz8hfSgvWfAEuD8qQPQOnI4v+K7jbMLsZUCS+HD6jT4QFmxp QKDaUzInOHKh0ME3pOqgys6XPYYJlKmvtJSeYBfy3m6uaPaMrLEd/1D8nmqlCSPCwFpo44t4OqM h6PNfypg5Tw0UAjzlgkExTn81Dg== X-Received: from ilkj13.prod.google.com ([2002:a05:6e02:eed:b0:500:7845:86d8]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6808:5146:b0:485:4f07:eefc with SMTP id 5614622812f47-4872de6bf08mr2751851b6e.15.1781292552277; Fri, 12 Jun 2026 12:29:12 -0700 (PDT) Date: Fri, 12 Jun 2026 19:28:50 +0000 In-Reply-To: <20260612192909.1153907-1-coltonlewis@google.com> Mime-Version: 1.0 References: <20260612192909.1153907-1-coltonlewis@google.com> X-Mailer: git-send-email 2.54.0.1136.gdb2ca164c4-goog Message-ID: <20260612192909.1153907-3-coltonlewis@google.com> Subject: [PATCH 02/21] KVM: arm64: Reorganize PMU includes From: Colton Lewis To: kvm@vger.kernel.org Cc: Alexandru Elisei , Paolo Bonzini , Jonathan Corbet , Russell King , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Mingwei Zhang , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mark Rutland , Shuah Khan , Ganapatrao Kulkarni , James Clark , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, Colton Lewis Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260612_122914_149251_449DD1B0 X-CRM114-Status: GOOD ( 13.59 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Marc Zyngier Including *all* of asm/kvm_host.h in asm/arm_pmuv3.h is a bad idea because that is much more than arm_pmuv3.h logically needs and creates a circular dependency that makes it easy to introduce compiler errors when editing this code. asm/kvm_host.h includes kvm/arm_pmu.h includes perf/arm_pmuv3.h includes asm/arm_pmuv3.h includes asm/kvm_host.h Reorganize the PMU includes to be more sane. In particular: * Remove the circular dependency by removing the kvm_host.h include from asm/arm_pmuv3.h since 99% of it isn't needed. * Move the remaining tiny bit of KVM/PMU interface from kvm_host.h into arm_pmu.h * Conditionally on ARM64, include the more targeted arm_pmu.h directly in the arm_pmuv3.c driver. Signed-off-by: Marc Zyngier Signed-off-by: Colton Lewis --- arch/arm64/include/asm/arm_pmuv3.h | 2 -- arch/arm64/include/asm/kvm_host.h | 14 -------------- drivers/perf/arm_pmuv3.c | 5 +++++ include/kvm/arm_pmu.h | 19 +++++++++++++++++++ 4 files changed, 24 insertions(+), 16 deletions(-) diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h index 8a777dec8d88a..cf2b2212e00a2 100644 --- a/arch/arm64/include/asm/arm_pmuv3.h +++ b/arch/arm64/include/asm/arm_pmuv3.h @@ -6,8 +6,6 @@ #ifndef __ASM_PMUV3_H #define __ASM_PMUV3_H -#include - #include #include diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h index a49042bfa801f..0d7a620c69ee2 100644 --- a/arch/arm64/include/asm/kvm_host.h +++ b/arch/arm64/include/asm/kvm_host.h @@ -1480,25 +1480,11 @@ void kvm_arch_vcpu_ctxflush_fp(struct kvm_vcpu *vcpu); void kvm_arch_vcpu_ctxsync_fp(struct kvm_vcpu *vcpu); void kvm_arch_vcpu_put_fp(struct kvm_vcpu *vcpu); -static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) -{ - return (!has_vhe() && attr->exclude_host); -} - #ifdef CONFIG_KVM -void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); -void kvm_clr_pmu_events(u64 clr); -bool kvm_set_pmuserenr(u64 val); void kvm_enable_trbe(void); void kvm_disable_trbe(void); void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest); #else -static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} -static inline void kvm_clr_pmu_events(u64 clr) {} -static inline bool kvm_set_pmuserenr(u64 val) -{ - return false; -} static inline void kvm_enable_trbe(void) {} static inline void kvm_disable_trbe(void) {} static inline void kvm_tracing_set_el1_configuration(u64 trfcr_while_in_guest) {} diff --git a/drivers/perf/arm_pmuv3.c b/drivers/perf/arm_pmuv3.c index 8014ff766cff5..8d3b832cd633a 100644 --- a/drivers/perf/arm_pmuv3.c +++ b/drivers/perf/arm_pmuv3.c @@ -9,6 +9,11 @@ */ #include + +#if defined(CONFIG_ARM64) +#include +#endif + #include #include diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 0a36a3d5c8944..ec74a58905712 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -9,12 +9,22 @@ #include #include +#include #define KVM_ARMV8_PMU_MAX_COUNTERS 32 /* PPI #23 - architecturally specified for GICv5 */ #define KVM_ARMV8_PMU_GICV5_IRQ 0x20000017 +#define kvm_pmu_counter_deferred(attr) \ + ({ \ + !has_vhe() && (attr)->exclude_host; \ + }) + +struct kvm; +struct kvm_device_attr; +struct kvm_vcpu; + #if IS_ENABLED(CONFIG_HW_PERF_EVENTS) && IS_ENABLED(CONFIG_KVM) struct kvm_pmc { u8 idx; /* index into the pmu->pmc array */ @@ -69,6 +79,9 @@ int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu); struct kvm_pmu_events *kvm_get_pmu_events(void); +void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr); +void kvm_clr_pmu_events(u64 clr); +bool kvm_set_pmuserenr(u64 val); void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu); void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu); void kvm_vcpu_pmu_resync_el0(void); @@ -162,6 +175,12 @@ static inline u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1) #define kvm_vcpu_has_pmu(vcpu) ({ false; }) static inline void kvm_pmu_update_vcpu_events(struct kvm_vcpu *vcpu) {} +static inline void kvm_set_pmu_events(u64 set, struct perf_event_attr *attr) {} +static inline void kvm_clr_pmu_events(u64 clr) {} +static inline bool kvm_set_pmuserenr(u64 val) +{ + return false; +} static inline void kvm_vcpu_pmu_restore_guest(struct kvm_vcpu *vcpu) {} static inline void kvm_vcpu_pmu_restore_host(struct kvm_vcpu *vcpu) {} static inline void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu) {} -- 2.54.0.1136.gdb2ca164c4-goog