From: gowtham <gowtham@ferryfair.com>
To: yue.wang@Amlogic.com, lpieralisi@kernel.org,
kwilczynski@kernel.org, mani@kernel.org
Cc: robh@kernel.org, bhelgaas@google.com, neil.armstrong@linaro.org,
khilman@baylibre.com, jbrunet@baylibre.com,
martin.blumenstingl@googlemail.com, linux-pci@vger.kernel.org,
linux-amlogic@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: [PULL] PCI: meson: Fix PERST# timing by asserting reset before LTSSM enable
Date: Sun, 14 Jun 2026 09:56:26 +0530 [thread overview]
Message-ID: <20260614095626.7afb7c04@slick.ferryfair.com> (raw)
The following changes since commit
bb532bfaf7919c7c98caab81864e9ce2646e11e3:
Linux 7.0.11 (2026-06-01 17:54:55 +0200)
are available in the Git repository at:
https://github.com/GowthamKudupudi/linux.git
tags/meson-pcie-warm-reset-linux-7.0.y
for you to fetch changes up to 852811b11795ee389ea6a953ed0db69b76722469:
PCI: meson: Fix PERST# timing by asserting reset before LTSSM enable
(2026-06-14 09:41:01 +0530)
----------------------------------------------------------------
PCI: meson: Fix PERST# timing by asserting reset before LTSSM enable
On warm reboot, the PCIe controller's LTSSM starts link training
immediately if PERST# is already deasserted from the previous boot.
The driver then pulses PERST# for only 500us, which is too short to
properly reset the endpoint device that has already started training.
Fix by moving the PERST# assert/deassert pulse BEFORE enabling LTSSM,
so the endpoint gets a clean reset cycle before link training begins.
This was found on Amlogic G12B (A311D) with NVMe on an M.2 slot.
Cold boot worked because POR held PERST# low; warm reboot did not.
The fix was confirmed on a Banana Pi CM4 with Waveshare IO base board.
----------------------------------------------------------------
Gowtham Kudupudi (1):
PCI: meson: Fix PERST# timing by asserting reset before LTSSM
enable
drivers/pci/controller/dwc/pci-meson.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
reply other threads:[~2026-06-14 4:26 UTC|newest]
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