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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-492201fad25sm242143105e9.0.2026.06.15.01.56.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 15 Jun 2026 01:56:17 -0700 (PDT) Date: Mon, 15 Jun 2026 09:56:16 +0100 From: David Laight To: Ethan Nelson-Moore Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org, Russell King , "Russell King (Oracle)" , Arnd Bergmann , Linus Walleij , Kees Cook , Nathan Chancellor , Thomas Weissschuh , Peter Zijlstra , Shubham Bansal , "David S. Miller" Subject: Re: [PATCH] ARM: disable broken eBPF JIT on the Risc PC Message-ID: <20260615095616.1c590e14@pumpkin> In-Reply-To: References: <20260518014920.135011-1-enelsonmoore@gmail.com> <20260614125857.398a0e13@pumpkin> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260615_015619_795946_F7220342 X-CRM114-Status: GOOD ( 17.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sun, 14 Jun 2026 14:44:38 -0700 Ethan Nelson-Moore wrote: > Hi, David, >=20 > On Sun, Jun 14, 2026 at 4:58=E2=80=AFAM David Laight > wrote: > > Isn't it more the case that the ldrh/strh instructions were added for a= rmv4. > > Whether the bus supports 16bit accesses is entirely different. =20 >=20 > No, it is in fact the bus. While the Risc PC initially shipped with > ARMv3 CPUs, which the kernel no longer supports, it was later upgraded > to an ARMv4 StrongARM CPU. However, its bus was designed for ARMv3 > CPUs and has no way to represent a half-word access to memory. This > means that ldrh/strh will execute (because the CPU supports them) but > do not function as intended. Ok, so they work fine for cached accesses. The only issue will be with uncached ones? (Or do I remember the strongarm having a write-through cache?) It just seems odd because byte writes are usually handled with four byte-enable lines; so the targets support all 16 combinations even though a cpu will (normally) only be able to generate 8 of them. David >=20 > Ethan