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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260616_132737_840466_34398FA1 X-CRM114-Status: GOOD ( 13.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This makes use of the driver added in the previous patches. It wires up the uart clocks and resets and allows getting rid of the placeholder uartclk node. Signed-off-by: Stefan Dösinger --- arch/arm/boot/dts/zte/zx297520v3.dtsi | 90 +++++++++++++++++++++++++++++++---- 1 file changed, 81 insertions(+), 9 deletions(-) diff --git a/arch/arm/boot/dts/zte/zx297520v3.dtsi b/arch/arm/boot/dts/zte/zx297520v3.dtsi index a16c30a164bb..a2b6909e7434 100644 --- a/arch/arm/boot/dts/zte/zx297520v3.dtsi +++ b/arch/arm/boot/dts/zte/zx297520v3.dtsi @@ -4,6 +4,7 @@ */ #include +#include / { #address-cells = <1>; @@ -20,13 +21,16 @@ cpu@0 { }; }; - /* Base bus clock and default for the UART. It will be replaced once a clock driver has - * been added. - */ - uartclk: uartclk-26000000 { - #clock-cells = <0>; + osc26m: osc26m { compatible = "fixed-clock"; clock-frequency = <26000000>; + #clock-cells = <0>; + }; + + osc32k: osc32k { + compatible = "fixed-clock"; + clock-frequency = <32768>; + #clock-cells = <0>; }; timer { @@ -70,13 +74,80 @@ gic: interrupt-controller@f2000000 { <0xf2040000 0x20000>; }; + topclk: clock-controller@13b000 { + compatible = "zte,zx297520v3-topclk", "syscon"; + reg = <0x0013b000 0x400>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&osc26m>, <&osc32k>; + clock-names = "osc26m", "osc32k"; + }; + + matrixclk: clock-controller@1306000 { + compatible = "zte,zx297520v3-matrixclk", "syscon"; + reg = <0x01306000 0x400>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&osc26m>, <&osc32k>, + <&topclk ZX297520V3_MPLL>, <&topclk ZX297520V3_MPLL_D2>, + <&topclk ZX297520V3_MPLL_D3>, <&topclk ZX297520V3_MPLL_D4>, + <&topclk ZX297520V3_MPLL_D5>, <&topclk ZX297520V3_MPLL_D6>, + <&topclk ZX297520V3_MPLL_D8>, <&topclk ZX297520V3_MPLL_D12>, + <&topclk ZX297520V3_MPLL_D16>, <&topclk ZX297520V3_MPLL_D26>, + <&topclk ZX297520V3_UPLL>, <&topclk ZX297520V3_UPLL_D2>, + <&topclk ZX297520V3_UPLL_D3>, <&topclk ZX297520V3_UPLL_D4>, + <&topclk ZX297520V3_UPLL_D5>, <&topclk ZX297520V3_UPLL_D6>, + <&topclk ZX297520V3_UPLL_D8>, <&topclk ZX297520V3_UPLL_D12>, + <&topclk ZX297520V3_UPLL_D16>, + <&topclk ZX297520V3_DPLL>, <&topclk ZX297520V3_DPLL_D2>, + <&topclk ZX297520V3_DPLL_D3>, <&topclk ZX297520V3_DPLL_D4>, + <&topclk ZX297520V3_DPLL_D5>, <&topclk ZX297520V3_DPLL_D6>, + <&topclk ZX297520V3_DPLL_D8>, <&topclk ZX297520V3_DPLL_D12>, + <&topclk ZX297520V3_DPLL_D16>, + <&topclk ZX297520V3_GPLL>, <&topclk ZX297520V3_GPLL_D2>, + <&topclk ZX297520V3_GPLL_D3>, <&topclk ZX297520V3_GPLL_D4>, + <&topclk ZX297520V3_GPLL_D5>, <&topclk ZX297520V3_GPLL_D6>, + <&topclk ZX297520V3_GPLL_D8>, <&topclk ZX297520V3_GPLL_D12>, + <&topclk ZX297520V3_GPLL_D16>; + clock-names = "osc26m", "osc32k", "mpll", "mpll_d2", "mpll_d3", "mpll_d4", + "mpll_d5", "mpll_d6", "mpll_d8", "mpll_d12", "mpll_d16", + "mpll_d26", "upll", "upll_d2", "upll_d3", "upll_d4", + "upll_d5", "upll_d6", "upll_d8", "upll_d12", "upll_d16", + "dpll", "dpll_d2", "dpll_d3", "dpll_d4", "dpll_d5", "dpll_d6", + "dpll_d8", "dpll_d12", "dpll_d16", "gpll", "gpll_d2", + "gpll_d3", "gpll_d4", "gpll_d5", "gpll_d6", "gpll_d8", + "gpll_d12", "gpll_d16"; + }; + + lspclk: clock-controller@1400000 { + compatible = "zte,zx297520v3-lspclk"; + reg = <0x01400000 0x100>; + #clock-cells = <1>; + #reset-cells = <1>; + + clocks = <&matrixclk ZX297520V3_LSP_MPLL_D5_WCLK>, + <&matrixclk ZX297520V3_LSP_MPLL_D4_WCLK>, + <&matrixclk ZX297520V3_LSP_MPLL_D6_WCLK>, + <&matrixclk ZX297520V3_LSP_MPLL_D8_WCLK>, + <&matrixclk ZX297520V3_LSP_MPLL_D12_WCLK>, + <&matrixclk ZX297520V3_LSP_OSC26M_WCLK>, + <&matrixclk ZX297520V3_LSP_OSC32K_WCLK>, + <&matrixclk ZX297520V3_LSP_PCLK>, + <&matrixclk ZX297520V3_LSP_TDM_WCLK>, + <&matrixclk ZX297520V3_LSP_DPLL_D4_WCLK>; + clock-names = "mpll_d5", "mpll_d4", "mpll_d6", "mpll_d8", "mpll_d12", + "osc26m", "osc32k", "pclk", "tdm_wclk", "dpll_d4"; + }; + + uart0: serial@131000 { compatible = "arm,pl011", "arm,primecell"; arm,primecell-periphid = <0x0018c011>; reg = <0x00131000 0x1000>; interrupts = ; - clocks = <&uartclk>, <&uartclk>; + clocks = <&topclk ZX297520V3_UART0_WCLK>, <&topclk ZX297520V3_UART0_PCLK>; clock-names = "uartclk", "apb_pclk"; + resets = <&topclk ZX297520V3_UART0_RESET>; status = "disabled"; }; @@ -85,8 +156,9 @@ uart1: serial@1408000 { arm,primecell-periphid = <0x0018c011>; reg = <0x01408000 0x1000>; interrupts = ; - clocks = <&uartclk>, <&uartclk>; + clocks = <&lspclk ZX297520V3_UART1_WCLK>, <&lspclk ZX297520V3_UART1_PCLK>; clock-names = "uartclk", "apb_pclk"; + resets = <&lspclk ZX297520V3_UART1_RESET>; status = "disabled"; }; @@ -94,9 +166,9 @@ uart2: serial@140d000 { compatible = "arm,pl011", "arm,primecell"; arm,primecell-periphid = <0x0018c011>; reg = <0x0140d000 0x1000>; - interrupts = ; - clocks = <&uartclk>, <&uartclk>; + clocks = <&lspclk ZX297520V3_UART2_WCLK>, <&lspclk ZX297520V3_UART2_PCLK>; clock-names = "uartclk", "apb_pclk"; + resets = <&lspclk ZX297520V3_UART2_RESET>; status = "disabled"; }; }; -- 2.53.0