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[47.54.130.67]) by smtp.gmail.com with ESMTPSA id af79cd13be357-920a424f817sm215731985a.22.2026.06.19.05.03.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 19 Jun 2026 05:03:10 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1waXwD-00000004SQK-4AfU; Fri, 19 Jun 2026 09:03:09 -0300 Date: Fri, 19 Jun 2026 09:03:09 -0300 From: Jason Gunthorpe To: Alexey Kardashevskiy Cc: "Aneesh Kumar K.V" , Catalin Marinas , iommu@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-coco@lists.linux.dev, Robin Murphy , Marek Szyprowski , Will Deacon , Marc Zyngier , Steven Price , Suzuki K Poulose , Jiri Pirko , Mostafa Saleh , Petr Tesarik , Dan Williams , Xu Yilun , linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, Madhavan Srinivasan , Michael Ellerman , Nicholas Piggin , "Christophe Leroy (CS GROUP)" , Alexander Gordeev , Gerald Schaefer , Heiko Carstens , Vasily Gorbik , Christian Borntraeger , Sven Schnelle , x86@kernel.org Subject: Re: [PATCH v6 00/20] dma-mapping: Use DMA_ATTR_CC_SHARED through direct, pool and swiotlb paths Message-ID: <20260619120309.GI231643@ziepe.ca> References: <20260604083959.1265923-1-aneesh.kumar@kernel.org> <20260609144746.GL2764304@ziepe.ca> <2ecfa1a8-6202-4319-9692-a6ffeb5a3dbf@amd.com> <20260618153705.GH231643@ziepe.ca> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260619_050314_117880_C3139435 X-CRM114-Status: GOOD ( 27.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jun 19, 2026 at 12:05:45PM +1000, Alexey Kardashevskiy wrote: > > > > > IMHO that's an AMD issue, not with the design of this series.. > > > > > > > > > > The series is right, a device that is !force_dma_decrypted() must be > > > > > considerd to be a trusted device and we must never place any DMA > > > > > mappings for a trusted device into shared memory. > > > > > > > > swiotlb=force forces swiotlb, not decryption. > > > > If force_dma_decrypted() == true then swiotlb must allocate from a > > decrypted memory pool. It is right there in the name! > > > > The hypervisor environment should *never* set force_dma_decrypted() > > because all devices can access all hypervisor memory, up to their IOVA > > limits. > > True. But we do not have encrypted swiotlb pool today, right? "encrypted" is just normal struct page memory, that's the default for swiotlb. I think it was a big mistake for the AMD SME stuff to overload the decrypted/encrypted CC stuff which should mean shared/private in a guest context to also mean things about physical memory encryption in the host. It is really confusing. The SME side is just a bad arch choice, the real world doesn't work well if you set high address bits in your dma_addr_t. I think AMD needs to use those restricted swiotlb pool where it allocates this very special "SME Disabled" memory that will have a low dma_addr_t. Then alloc and bouncing will get memory with a suitable dma_addr_t. This has nothing to do with force_dma_unencrypted() which is only a CC guest concept and nothing else in the OS should ever touch decrypted memory. > > And this is more insane logic. The right fix is to allocate the > > swiotlb bounce from the *encrypted* pools when running on the > > hypervisor which requires undoing this abuse of force_dma_decrypted(). > > +1. > > But how does the kernel decide if it is this swiotlb pool or just > some page which happens to be below the IOVA limit? You mean in swiotlb_tbl_unmap_single() ? It checks the address against the pool's range? > swiotlb can be for bouncing (with all these dma_sync_single_for_cpu) > or, if dev->dma_io_tlb_mem->for_alloc = true, for coherent > allocation (no need in dma_sync_single_for_cpu). > > I am looking for a way to set up my "sev-guest" device such as when Whats a "sev-guest" device? > dma_alloc_attrs(snp_dev->dev,...) happens, it allocates a page from > the shared swiotlb pool (with no actual bouncing) and there is no > obvious way to trick the DMA layer into doing that. Why do you need this? Jason