From: Joshua Liu <josliu@google.com>
To: catalin.marinas@arm.com
Cc: linux-arm-kernel@lists.infradead.org, will@kernel.org,
Joshua Liu <josliu@google.com>
Subject: Re: [PATCH] arm64: Avoid eager DVMSync reclaim batches with C1-Pro SME erratum
Date: Mon, 22 Jun 2026 12:52:27 +0000 [thread overview]
Message-ID: <20260622125227.877198-1-josliu@google.com> (raw)
In-Reply-To: <20260610104829.1157497-1-catalin.marinas@arm.com>
On Wed, Jun 10, 2026 at 11:37 AM Catalin Marinas <catalin.marinas@arm.com> wrote:
> Introduce the sme_active_cpus mask tracking which CPUs run in user-space
> with SME enabled and use it for batch flushing instead of accumulating
> the mm_cpumask() of the unmapped pages.
> [...]
> The dsb() in arch_tlbbatch_add_pending() -> sme_dvmsync_add_pending()
> did introduce a performance regression for kswapd. This patch restores
> the original behaviour with the barrier only issued when the TLB batch
> is flushed. The trade-off is that the IPIs are now sent to all CPUs
> running with SME enabled at EL0 even if the reclaimed pages do not
> belong to SME tasks. This is acceptable for current SME deployments.
Profiling shows this solution has robust performance for common
workloads and is the best among a few approaches we tested with Catalin,
so we are happy to go with this solution.
Some sidenotes: for certain edge cases we still observe performance
regression, specifically when a workload pegs multiple cores with SME
status threads.
Tested-by: Joshua Liu <josliu@google.com>
next prev parent reply other threads:[~2026-06-22 12:52 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-10 10:37 [PATCH] arm64: Avoid eager DVMSync reclaim batches with C1-Pro SME erratum Catalin Marinas
2026-06-18 16:54 ` Will Deacon
2026-06-22 12:52 ` Joshua Liu [this message]
2026-06-23 11:59 ` Will Deacon
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