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Sun, 28 Jun 2026 12:59:26 -0700 (PDT) Received: from [192.168.0.2] ([197.250.51.120]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-493ae96c85fsm15133505e9.5.2026.06.28.12.59.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 28 Jun 2026 12:59:26 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Date: Sun, 28 Jun 2026 22:58:57 +0300 Subject: [PATCH RFC v5 02/12] dt-bindings: soc: zte: Add zx297520v3 matrix clock and reset bindings MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Message-Id: <20260628-zx29clk-v5-2-79ff044e4192@gmail.com> References: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com> In-Reply-To: <20260628-zx29clk-v5-0-79ff044e4192@gmail.com> To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260628_125928_860608_BFE2243C X-CRM114-Status: GOOD ( 15.61 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This controller contains clocks and resets for high speed devices on the zx297520v3 board and hardware spinlocks that I expect will be necessary to communicate correctly with the LTE DSP firmware blob. A simple MFD driver will instantiate independent clock, reset and hwlock drivers. Signed-off-by: Stefan Dösinger --- Changes v4->v5: Move binding to soc/zte Remove topclk from the example Add #hwlock-cells for hw spinlock registers Add more clocks I stumbled into: sram0 and another LTE related device v3->v4: Split matrixclk into its own controller again because syscon/regmap deals poorly with device nodes that have more than one memory region. As a consequence I am passing all PLL outputs generated on Topclk down to Matrixclk. --- .../bindings/soc/zte/zte,zx297520v3-matrixcrm.yaml | 177 +++++++++++++++++++++ include/dt-bindings/clock/zte,zx297520v3-clk.h | 37 +++++ include/dt-bindings/reset/zte,zx297520v3-reset.h | 10 ++ 3 files changed, 224 insertions(+) diff --git a/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-matrixcrm.yaml b/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-matrixcrm.yaml new file mode 100644 index 000000000000..bbec0eb837da --- /dev/null +++ b/Documentation/devicetree/bindings/soc/zte/zte,zx297520v3-matrixcrm.yaml @@ -0,0 +1,177 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/zte/zte,zx297520v3-matrixcrm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ZTE zx297520v3 SoC matrix clock and reset controller + +maintainers: + - Stefan Dösinger + +description: | + This controller contains clock and reset controls for high speed devices on + the zx297520v3 board: The CPU, RAM, SDIO and Ethernet clocks and resets are + found here. This controller requires PLL-generated clocks from Topcrm as well + as the fixed 26 MHz and 32 KHz oscillators found on this board. + + This controller also contains hardware mutex registers for synchronization + with different processors on this board. + + All available clocks are defined as preprocessor macros in the + 'dt-bindings/clock/zte,zx297520v3-clk.h' header. Resets are defined in the + 'dt-bindings/reset/zte,zx297520v3-reset.h' header. + +properties: + compatible: + items: + - const: zte,zx297520v3-matrixcrm + + reg: + maxItems: 1 + + clocks: + items: + - description: 26 MHz external oscillator + - description: 32 KHz external oscillator + - description: Main PLL output from topcrm (usually 624 MHz) + - description: Main PLL subdivision factor 2 + - description: Main PLL subdivision factor 3 + - description: Main PLL subdivision factor 4 + - description: Main PLL subdivision factor 5 + - description: Main PLL subdivision factor 6 + - description: Main PLL subdivision factor 8 + - description: Main PLL subdivision factor 12 + - description: Main PLL subdivision factor 16 + - description: Main PLL subdivision factor 26 + - description: Upll output from topcrm (Usually 480 MHz) + - description: Upll subdivision factor 2 + - description: Upll subdivision factor 3 + - description: Upll subdivision factor 4 + - description: Upll subdivision factor 5 + - description: Upll subdivision factor 6 + - description: Upll subdivision factor 8 + - description: Upll subdivision factor 12 + - description: Upll subdivision factor 16 + - description: Dpll output from topcrm (usually 492.88 MHz) + - description: Dpll subdivision factor 2 + - description: Dpll subdivision factor 3 + - description: Dpll subdivision factor 4 + - description: Dpll subdivision factor 5 + - description: Dpll subdivision factor 6 + - description: Dpll subdivision factor 8 + - description: Dpll subdivision factor 12 + - description: Dpll subdivision factor 16 + - description: Gpll output from topcrm (usually 200 MHz) + - description: Gpll subdivision factor 2 + - description: Gpll subdivision factor 3 + - description: Gpll subdivision factor 4 + - description: Gpll subdivision factor 5 + - description: Gpll subdivision factor 6 + - description: Gpll subdivision factor 8 + - description: Gpll subdivision factor 12 + - description: Gpll subdivision factor 16 + + clock-names: + items: + - const: osc26m + - const: osc32k + - const: mpll + - const: mpll_d2 + - const: mpll_d3 + - const: mpll_d4 + - const: mpll_d5 + - const: mpll_d6 + - const: mpll_d8 + - const: mpll_d12 + - const: mpll_d16 + - const: mpll_d26 + - const: upll + - const: upll_d2 + - const: upll_d3 + - const: upll_d4 + - const: upll_d5 + - const: upll_d6 + - const: upll_d8 + - const: upll_d12 + - const: upll_d16 + - const: dpll + - const: dpll_d2 + - const: dpll_d3 + - const: dpll_d4 + - const: dpll_d5 + - const: dpll_d6 + - const: dpll_d8 + - const: dpll_d12 + - const: dpll_d16 + - const: gpll + - const: gpll_d2 + - const: gpll_d3 + - const: gpll_d4 + - const: gpll_d5 + - const: gpll_d6 + - const: gpll_d8 + - const: gpll_d12 + - const: gpll_d16 + + "#clock-cells": + const: 1 + + "#hwlock-cells": + const: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#clock-cells' + - "#hwlock-cells" + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + #include + + clock-controller@1306000 { + compatible = "zte,zx297520v3-matrixcrm"; + reg = <0x01306000 0x400>; + clocks = <&osc26m>, <&osc32k>, + <&topcrm ZX297520V3_MPLL>, <&topcrm ZX297520V3_MPLL_D2>, + <&topcrm ZX297520V3_MPLL_D3>, <&topcrm ZX297520V3_MPLL_D4>, + <&topcrm ZX297520V3_MPLL_D5>, <&topcrm ZX297520V3_MPLL_D6>, + <&topcrm ZX297520V3_MPLL_D8>, <&topcrm ZX297520V3_MPLL_D12>, + <&topcrm ZX297520V3_MPLL_D16>, <&topcrm ZX297520V3_MPLL_D26>, + <&topcrm ZX297520V3_UPLL>, <&topcrm ZX297520V3_UPLL_D2>, + <&topcrm ZX297520V3_UPLL_D3>, <&topcrm ZX297520V3_UPLL_D4>, + <&topcrm ZX297520V3_UPLL_D5>, <&topcrm ZX297520V3_UPLL_D6>, + <&topcrm ZX297520V3_UPLL_D8>, <&topcrm ZX297520V3_UPLL_D12>, + <&topcrm ZX297520V3_UPLL_D16>, + <&topcrm ZX297520V3_DPLL>, <&topcrm ZX297520V3_DPLL_D2>, + <&topcrm ZX297520V3_DPLL_D3>, <&topcrm ZX297520V3_DPLL_D4>, + <&topcrm ZX297520V3_DPLL_D5>, <&topcrm ZX297520V3_DPLL_D6>, + <&topcrm ZX297520V3_DPLL_D8>, <&topcrm ZX297520V3_DPLL_D12>, + <&topcrm ZX297520V3_DPLL_D16>, + <&topcrm ZX297520V3_GPLL>, <&topcrm ZX297520V3_GPLL_D2>, + <&topcrm ZX297520V3_GPLL_D3>, <&topcrm ZX297520V3_GPLL_D4>, + <&topcrm ZX297520V3_GPLL_D5>, <&topcrm ZX297520V3_GPLL_D6>, + <&topcrm ZX297520V3_GPLL_D8>, <&topcrm ZX297520V3_GPLL_D12>, + <&topcrm ZX297520V3_GPLL_D16>; + clock-names = "osc26m", "osc32k", "mpll", "mpll_d2", "mpll_d3", + "mpll_d4", "mpll_d5", "mpll_d6", "mpll_d8", "mpll_d12", + "mpll_d16", "mpll_d26", "upll", "upll_d2", "upll_d3", + "upll_d4", "upll_d5", "upll_d6", "upll_d8", "upll_d12", + "upll_d16", "dpll", "dpll_d2", "dpll_d3", "dpll_d4", + "dpll_d5", "dpll_d6", "dpll_d8", "dpll_d12", "dpll_d16", + "gpll", "gpll_d2", "gpll_d3", "gpll_d4", "gpll_d5", + "gpll_d6", "gpll_d8", "gpll_d12", "gpll_d16"; + #clock-cells = <1>; + #hwlock-cells = <1>; + #reset-cells = <1>; + }; diff --git a/include/dt-bindings/clock/zte,zx297520v3-clk.h b/include/dt-bindings/clock/zte,zx297520v3-clk.h index de1c08b6a5a9..8a6aa456a708 100644 --- a/include/dt-bindings/clock/zte,zx297520v3-clk.h +++ b/include/dt-bindings/clock/zte,zx297520v3-clk.h @@ -94,4 +94,41 @@ #define ZX297520V3_HSIC_WCLK 86 #define ZX297520V3_HSIC_PCLK 87 +#define ZX297520V3_CPU_WCLK 1 +#define ZX297520V3_CPU_PCLK 2 +#define ZX297520V3_ZSP_WCLK 3 +#define ZX297520V3_EDCP_WCLK 4 +#define ZX297520V3_EDCP_PCLK 5 +#define ZX297520V3_SD0_WCLK 6 +#define ZX297520V3_SD0_PCLK 7 +#define ZX297520V3_SD0_CDET 8 +#define ZX297520V3_SD1_WCLK 9 +#define ZX297520V3_SD1_PCLK 10 +#define ZX297520V3_SD1_CDET 11 +#define ZX297520V3_NAND_WCLK 12 +#define ZX297520V3_NAND_PCLK 13 +#define ZX297520V3_DMA_PCLK 14 +#define ZX297520V3_MBOX_PCLK 15 +#define ZX297520V3_PDCFG_WCLK 16 +#define ZX297520V3_PDCFG_PCLK 17 +#define ZX297520V3_SSC_WCLK 18 +#define ZX297520V3_SSC_PCLK 19 +#define ZX297520V3_GMAC_WCLK 20 +#define ZX297520V3_GMAC_PCLK 21 +#define ZX297520V3_GMAC_AHB 22 +#define ZX297520V3_VOU_WCLK 23 +#define ZX297520V3_VOU_PCLK 24 +#define ZX297520V3_LSP_MPLL_D5_WCLK 25 +#define ZX297520V3_LSP_MPLL_D4_WCLK 26 +#define ZX297520V3_LSP_MPLL_D6_WCLK 27 +#define ZX297520V3_LSP_MPLL_D8_WCLK 28 +#define ZX297520V3_LSP_MPLL_D12_WCLK 29 +#define ZX297520V3_LSP_OSC26M_WCLK 30 +#define ZX297520V3_LSP_OSC32K_WCLK 31 +#define ZX297520V3_LSP_PCLK 32 +#define ZX297520V3_LSP_TDM_WCLK 33 +#define ZX297520V3_LSP_DPLL_D4_WCLK 34 +#define ZX297520V3_SRAM0_PCLK 35 +#define ZX297520V3_GSM_CFG_PCLK 36 + #endif /* __DT_BINDINGS_CLOCK_ZX297520V3_H */ diff --git a/include/dt-bindings/reset/zte,zx297520v3-reset.h b/include/dt-bindings/reset/zte,zx297520v3-reset.h index 43db72bb59de..81ffc8bc34c5 100644 --- a/include/dt-bindings/reset/zte,zx297520v3-reset.h +++ b/include/dt-bindings/reset/zte,zx297520v3-reset.h @@ -29,4 +29,14 @@ #define ZX297520V3_HSIC_PHY_RESET 20 #define ZX297520V3_HSIC_RESET 21 +#define ZX297520V3_CPU_RESET 0 +#define ZX297520V3_EDCP_RESET 1 +#define ZX297520V3_SD0_RESET 2 +#define ZX297520V3_SD1_RESET 3 +#define ZX297520V3_NAND_RESET 4 +#define ZX297520V3_PDCFG_RESET 5 +#define ZX297520V3_SSC_RESET 6 +#define ZX297520V3_GMAC_RESET 7 +#define ZX297520V3_VOU_RESET 8 + #endif /* __DT_BINDINGS_RESET_ZX297520V3_H */ -- 2.53.0