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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SN1PEPF0002636D.mail.protection.outlook.com (10.167.241.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.181.6 via Frontend Transport; Tue, 30 Jun 2026 04:56:56 +0000 Received: from BLRKPRNAYAK.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Mon, 29 Jun 2026 23:56:50 -0500 From: K Prateek Nayak To: Arnd Bergmann , Thomas Gleixner , "Ingo Molnar" , Peter Zijlstra , "Sebastian Andrzej Siewior" , Catalin Marinas , Will Deacon CC: Darren Hart , Davidlohr Bueso , =?UTF-8?q?Andr=C3=A9=20Almeida?= , , , Samuel Holland , Charlie Jenkins , "K Prateek Nayak" , , , , Jisheng Zhang Subject: [PATCH v5 3/8] arm64/runtime-const: Introduce runtime_const_mask_32() Date: Tue, 30 Jun 2026 04:55:26 +0000 Message-ID: <20260630045531.3939-4-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260630045531.3939-1-kprateek.nayak@amd.com> References: <20260630045531.3939-1-kprateek.nayak@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.180.168.240] X-ClientProxiedBy: satlexmb07.amd.com (10.181.42.216) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF0002636D:EE_|SJ2PR12MB8061:EE_ X-MS-Office365-Filtering-Correlation-Id: 465e43d2-2412-49a4-1e7c-08ded66402a0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|82310400026|7416014|23010399003|1800799024|3023799007|6133799003|56012099006|11063799006|13003099007|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tiAvd51zvr+0Du+widjlElD7vE2rKcdoQiw+Wr9AdU9cwnaCPhyRw8HjTUNy3FWXSBJkskZWJDladZ9b9QU9IAAp/fbWhCB+hL7YQIM9OytB66H//tHYT0o5vKMSda4SOQP4B8ePqS1hCcbShackGF/wXZnJLkFg2clzPezfA5nVHq6aw32AFVjqzIwz2PXrLt4OJMw6TUB8ZxgisEQktGE08YeMd7i3qNZimWJppPM//I5/cfRWLqRJOvdiz1yJ3cPadfaHU4bZ1jSa94S0g/0GtXLYckragF481YBRBWbUDFCsv9lGmVyHVkYDxR9w+YYes7Cb6oVnHdYfBfUE4SlKquS8rIgzTEvy556SFBSmCo2Fokb4ik1OnrAn8iRbJDQr0yYQPv75LtJniNLI4jQ4msCq3vcgfNQcjv9ebUoREe6VEDloDu7ZNARiKDLb X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jun 2026 04:56:56.1682 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 465e43d2-2412-49a4-1e7c-08ded66402a0 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF0002636D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8061 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260629_215704_188335_F8438132 X-CRM114-Status: GOOD ( 18.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Futex hash computation requires a mask operation with read-only after init data that will be converted to a runtime constant in the subsequent commit. Introduce runtime_const_mask_32 to further optimize the mask operation in the futex hash computation hot path. Since all the current use-cases are of the form GENMASK(n, 0), with n > 0, a single: ubfx w0, w0, #0, #widthm1 // w0 = w0 [widthm1:0] instruction is used for amd64 to improve instruction dinsity and performance. "Arm A-profile A64 Instruction Set Architecture" manual, Sec. "A64 -- Base Instructions" [1] for UBFX instruction highlights the immediate "width" is encoded as width minus 1 in imms (Bits [15:10]) which is patched by __runtime_fixup_mask() once the mask is known. If a future use case arises that needs to tackle arbitrary mask, consider using: movz w1, #lo16, lsl #0 movk w1, #hi16, lsl #16 to patch the 32-bit mask in the asm block and return "__ret & (val)" from runtime_const_mask_32() which allows compiler to further optimize the logical and operation. __runtime_fixup_ptr() already patches a "movz, + movk lsl #16" sequence which can be reused when the need arises. A possible implementation for this alternate scheme can be found at [2]. Assisted-by: Claude:claude-sonnet-4-6 Suggested-by: Samuel Holland Suggested-by: Charlie Jenkins Link: https://developer.arm.com/documentation/ddi0602/2026-03/Base-Instructions/ [1] Link: https://lore.kernel.org/lkml/20260430094730.31624-4-kprateek.nayak@amd.com/ [2] Signed-off-by: K Prateek Nayak --- changelog v4..v5: o Pivoted to using the UBFX instruction for masking since the futex use-case use masks of form 2^n - 1 (n > 1) since there was enough interest to improve instruction density for ARM64 and RISC-V. (Charlie, Samuel on v2) o Dropped Catalin's tag as a result of changed approach. --- arch/arm64/include/asm/runtime-const.h | 46 ++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/include/asm/runtime-const.h b/arch/arm64/include/asm/runtime-const.h index 838145bc289d2..371c9a4bc2d4b 100644 --- a/arch/arm64/include/asm/runtime-const.h +++ b/arch/arm64/include/asm/runtime-const.h @@ -36,6 +36,17 @@ :"r" (0u+(val))); \ __ret; }) +#define runtime_const_mask_32(val, sym) ({ \ + unsigned long __ret; \ + asm_inline("1:\t" \ + "ubfx %w0, %w1, #0, #32\n\t" \ + ".pushsection runtime_mask_" #sym ",\"a\"\n\t" \ + ".long 1b - .\n\t" \ + ".popsection" \ + :"=r" (__ret) \ + :"r" (0u+(val))); \ + __ret; }) + #define runtime_const_init(type, sym) do { \ extern s32 __start_runtime_##type##_##sym[]; \ extern s32 __stop_runtime_##type##_##sym[]; \ @@ -73,6 +84,41 @@ static inline void __runtime_fixup_shift(void *where, unsigned long val) aarch64_insn_patch_text_nosync(p, insn); } +static inline void __runtime_fixup_mask(void *where, unsigned long val) +{ + unsigned int width = __fls(val) + 1; + __le32 *p = where; + u32 insn; + + /* + * XXX: Current implementation only supports patching masks of + * form GENMASK(n, 0) (n >= 0) using a single UBFX instruction + * to improve performance, density, and covers all the current + * use-cases. + * + * When the need arises to support any generic mask, and this + * BUG_ON() is tripped, consider using a: + * + * movz %w0, #imm16 + * movk %w0, #imm16, lsl #16 + * + * sequence to load the 32bit const mask, and perform a logical + * and outside the asm block before returning the result. Fixup + * can simply reuse the existing __runtime_fixup_16() to patch + * the individual mov instructions. + */ + BUG_ON(!val || width > 32 || (GENMASK(width - 1, 0) != val)); + + /* + * The width of the mask is encoded as (width - 1) in imms + * which is 6 bits starting at bit #10. + */ + insn = le32_to_cpu(*p); + insn &= 0xffff03ff; + insn |= ((width - 1) & 0x1f) << 10; + aarch64_insn_patch_text_nosync(p, insn); +} + static inline void runtime_const_fixup(void (*fn)(void *, unsigned long), unsigned long val, s32 *start, s32 *end) { -- 2.34.1