From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 0DA05C43458 for ; Wed, 1 Jul 2026 08:48:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To:In-Reply-To:References :Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=+BZzbITC0E4sK8QIC43hKZGtTowm2ni8ynKK2Oo4rf0=; b=iFOkp2lbSG8v/rVLNt7GAmVA0I wGYSmYD5ibBr2F84Xx54k3f6az74XgRpLDz7ch12W/sUYv3R1lsiZmWOPXY+Avm5unvhLng1u9t7W 6Q/JmtgL3R0T76b/QNaryKoUIRaGdyeDi16YNl0AoubK9rzrgKCRhgawVU2ozhqogp8NUNFELc+ex 0wR8FeJiMJfain18+tJvJS4+sRw5EMoT9Me/O3Rtdw16+sIDrF0jj6yIWQTzxzQN610mPBcw6Mqz5 ft7oAuahdMcnRpDOfaMQGO3ysTdUcAas3pr1n5TTtPz9TXhfJuXswP1wSe3pBD3+EBfxxMIzu+jhG 4iVrSrLA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1weqcS-000000015K3-2nk7; Wed, 01 Jul 2026 08:48:32 +0000 Received: from desiato.infradead.org ([2001:8b0:10b:1:d65d:64ff:fe57:4e05]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1weqcR-000000015H8-0nDv for linux-arm-kernel@bombadil.infradead.org; Wed, 01 Jul 2026 08:48:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=infradead.org; s=desiato.20200630; h=Cc:To:In-Reply-To:References: Message-Id:Content-Transfer-Encoding:Content-Type:MIME-Version:Subject:Date: From:Sender:Reply-To:Content-ID:Content-Description; bh=+BZzbITC0E4sK8QIC43hKZGtTowm2ni8ynKK2Oo4rf0=; b=qSRVJj2rOPtL+pBBc+yhk0M3/8 Dm4WUv0krFFNQzQ0PUspqSYkNfoFxbE4A91JFWuRyKlvmLI1Oy5fVRtwP+8TTQfG08EmzMeqqNFvD PbBMCEnijUqRCp1y3OJSoNEkPshsPHZ1CEOhqwxrxTzr86gQNB0SiusFU/wu3fh13P+/ApeKAbkvs 9OGcVmNPVcaWXOJHEctX1W7VtGHiMkAuxrJ9vM+5zGkh/qNcuTxnaKa20dPOIh6IWnX+uxYRoVPd7 gguU/n8E6PEd0YT5UnRqIn84mcyrAmgsPx4Ylq/KEs6w0hfMiRlQzLhc78Imrh/jTMwPt/V4A97Y1 jKeBNgIA==; Received: from out-183.mta1.migadu.com ([95.215.58.183]) by desiato.infradead.org with esmtps (Exim 4.99.2 #2 (Red Hat Linux)) id 1weqcL-00000002WlE-0ysp for linux-arm-kernel@lists.infradead.org; Wed, 01 Jul 2026 08:48:26 +0000 X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1782895703; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+BZzbITC0E4sK8QIC43hKZGtTowm2ni8ynKK2Oo4rf0=; b=jT4yqzK8h5SQM2MrxoYQcWfzv7NkZ8DTVFazZyRncW6Dhye6jut6jLOPubxu/Vp0ncTSZ7 8J/8GHrnabvVZ1665K57gB+8QOFc5rLjVgX06yoigEZq7Act35Y27NDMZRNEag7uLyrDGG fR1b5GFTCxr/hU1DAajON0ngtqvOMQY= From: Atish Patra Date: Wed, 01 Jul 2026 01:47:01 -0700 Subject: [PATCH v8 13/22] RISC-V: perf: Add a mechanism to defined legacy event encoding MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260701-counter_delegation-v8-13-7909f863a645@meta.com> References: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> In-Reply-To: <20260701-counter_delegation-v8-0-7909f863a645@meta.com> To: Jiri Olsa , Paul Walmsley , Mark Rutland , Rob Herring , Anup Patel , Namhyung Kim , Arnaldo Carvalho de Melo , Krzysztof Kozlowski , Atish Patra , Ian Rogers , Will Deacon , James Clark Cc: linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-perf-users@vger.kernel.org, Conor Dooley X-Migadu-Flow: FLOW_OUT X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260701_094825_425341_B063A8CF X-CRM114-Status: GOOD ( 16.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Atish Patra RISC-V ISA doesn't define any standard event encodings or specify any event to counter mapping. Thus, event encoding information and corresponding counter mapping fot those events needs to be provided in the driver for each vendor. Add a framework to support that. The individual platform events will be added later. Signed-off-by: Atish Patra --- drivers/perf/riscv_pmu_sbi.c | 70 +++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 69 insertions(+), 1 deletion(-) diff --git a/drivers/perf/riscv_pmu_sbi.c b/drivers/perf/riscv_pmu_sbi.c index c20f1e33c65d..2568c6808f5d 100644 --- a/drivers/perf/riscv_pmu_sbi.c +++ b/drivers/perf/riscv_pmu_sbi.c @@ -10,6 +10,7 @@ #define pr_fmt(fmt) "riscv-pmu-sbi: " fmt +#include #include #include #include @@ -379,6 +380,71 @@ static int pmu_sbi_check_event_info(void) return result; } +/* + * Vendor specific PMU events. + */ +struct riscv_pmu_event { + u64 event_id; + u32 counter_mask; +}; + +#define HW_OP_UNSUPPORTED U64_MAX +#define CACHE_OP_UNSUPPORTED U64_MAX + +#define PERF_MAP_ALL_UNSUPPORTED \ + [0 ... PERF_COUNT_HW_MAX - 1] = {HW_OP_UNSUPPORTED, 0x0} + +#define PERF_CACHE_MAP_ALL_UNSUPPORTED \ +[0 ... PERF_COUNT_HW_CACHE_MAX - 1] = { \ + [0 ... PERF_COUNT_HW_CACHE_OP_MAX - 1] = { \ + [0 ... PERF_COUNT_HW_CACHE_RESULT_MAX - 1] = { \ + CACHE_OP_UNSUPPORTED, 0x0 \ + }, \ + }, \ +} + +struct riscv_vendor_pmu_events { + unsigned long vendorid; + unsigned long archid; + unsigned long implid; + const struct riscv_pmu_event *hw_event_map; + const struct riscv_pmu_event (*cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; +}; + +#define RISCV_VENDOR_PMU_EVENTS(_vendorid, _archid, _implid, _hw_event_map, _cache_event_map) \ + { .vendorid = _vendorid, .archid = _archid, .implid = _implid, \ + .hw_event_map = _hw_event_map, .cache_event_map = _cache_event_map }, + +static struct riscv_vendor_pmu_events pmu_vendor_events_table[] = { +}; + +static const struct riscv_pmu_event *current_pmu_hw_event_map; +static const struct riscv_pmu_event (*current_pmu_cache_event_map)[PERF_COUNT_HW_CACHE_OP_MAX] + [PERF_COUNT_HW_CACHE_RESULT_MAX]; + +static void __init rvpmu_vendor_register_events(void) +{ + int cpu = raw_smp_processor_id(); + unsigned long vendor_id = riscv_cached_mvendorid(cpu); + unsigned long impl_id = riscv_cached_mimpid(cpu); + unsigned long arch_id = riscv_cached_marchid(cpu); + + for (int i = 0; i < ARRAY_SIZE(pmu_vendor_events_table); i++) { + if (pmu_vendor_events_table[i].vendorid == vendor_id && + pmu_vendor_events_table[i].implid == impl_id && + pmu_vendor_events_table[i].archid == arch_id) { + current_pmu_hw_event_map = pmu_vendor_events_table[i].hw_event_map; + current_pmu_cache_event_map = pmu_vendor_events_table[i].cache_event_map; + break; + } + } + + if (!current_pmu_hw_event_map || !current_pmu_cache_event_map) { + pr_info("No default PMU events found\n"); + } +} + static void rvpmu_sbi_check_event(struct sbi_pmu_event_data *edata) { struct sbiret ret; @@ -1670,8 +1736,10 @@ static int __init rvpmu_devinit(void) */ if (riscv_isa_extension_available(NULL, SSCCFG) && riscv_isa_extension_available(NULL, SMCDELEG) && - riscv_isa_extension_available(NULL, SSCSRIND)) + riscv_isa_extension_available(NULL, SSCSRIND)) { static_branch_enable(&riscv_pmu_cdeleg_available); + rvpmu_vendor_register_events(); + } if (!(riscv_pmu_sbi_available_boot() || riscv_pmu_cdeleg_available_boot())) return 0; -- 2.53.0-Meta