From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id CA3CAC43327 for ; Wed, 1 Jul 2026 13:11:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Cc:To: Content-Transfer-Encoding:Content-Type:MIME-Version:Message-Id:Date:Subject: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References: List-Owner; bh=YOMYfvgj8yW4Pi/ltVPNg/vq+kvQKnAhZDTE4qutt1I=; b=U/FQ4iwI+Cjhf1 0Cn9WrKzzlWMT6VS9DcH6H2H4zIoLi5yOQG2RZwcfCQMYULPtgG8glH+WCzAPgs0Zh+UnhGPOs9zi FNyhFcVgKI1e52qo33W4hTQ3CDzU3EmvFAJklQsbtVsH5d7oBSthW9sP0sEgQPJ/+OE924nRAaxwc iPi0Njor9reIdYou6HafmtCO9vjvMISXTz5n1rSfgmVVQJUSYo93K6xbRWNC84rEcRZmliUx2ppmx 7T/0608NE2e4m+/enCYSQlkLebbc6Hz8qNHZlwsO+BbVDTUZVX6yTqWge42zS98pPF4QxtG6aDWZ6 5I6xq3EIBxjAVFJP/rOg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1weuip-000000027Vr-2xLK; Wed, 01 Jul 2026 13:11:23 +0000 Received: from bali.collaboradmins.com ([148.251.105.195]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1weuin-000000027V1-176P; Wed, 01 Jul 2026 13:11:22 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1782911478; bh=QIxKF0eP1N9vophR0MT1mP0a00BGi/R2xAljGm0nClI=; h=From:Subject:Date:To:Cc:From; b=hY0yNAyENtU/BPDjFqBMzUvBArPfg8rFQE7Ao9LMEhM3qBg0XylsoBpUbPpsKP/U8 DM8w7VsHwSznUTFlFN0QSQOTW/q/+k7A6Vpzr9wpd0AQ69LZpIg5gAUz+VceTGBFy7 Yk15qH+QnAPDaynqBOSRGEZa1bK78mUaKszOkCD81d3FntYt7fxvQ9v/Wf+6rJtU9C khhoaZ4DtjjmJhI6mWupLB+hh18f1lOKiGGmomDKrLqfXbZdjMsNoAeJEQr4gU734h MwcLhUpSoSPK5/9tj7wQktVF62ALUpREI/myOvspiXgczlRs9qRwPS65H2XZta8KzA tymUaDFwuzvHQ== Received: from yukiji.home (unknown [100.64.0.131]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: laeyraud) by bali.collaboradmins.com (Postfix) with ESMTPSA id B636A17E0CA2; Wed, 1 Jul 2026 15:11:17 +0200 (CEST) From: Louis-Alexis Eyraud Subject: [PATCH 00/15] MT8189: Add support for system and base clock controllers Date: Wed, 01 Jul 2026 15:11:05 +0200 Message-Id: <20260701-mt8189-clocks-system-base-v1-0-2b048feea50a@collabora.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/zWNQQ7CIBBFr0Jm7SSATVt7FdMF4qBEAcugqWl6d 0kbl+8n778FmLInhkEskOnj2adYQR0E2LuJN0J/rQxa6la2R4mh9Ko/oX0m+2DkLxcKeDFM2Ml ONdQ4p42B6r8yOT9v3+dx50zTuybKPsKm2RSCL4OINBf8Z2Bc1x+8LNctnAAAAA== X-Change-ID: 20260630-mt8189-clocks-system-base-70714e4ff2aa To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Philipp Zabel , Edward-JW Yang , Richard Cochran Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, Louis-Alexis Eyraud , Irving-CH Lin X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1782911477; l=6133; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=QIxKF0eP1N9vophR0MT1mP0a00BGi/R2xAljGm0nClI=; b=FdeE+8779Wq/oPJZpNVjjjWbQY4g2eRPA17K9WqARCgWMQnlsWZYkaCB7i4UMR5508qwj9uLr 5dQvAG4F5yyDpuCEms1WonOcn1eOhQUl3Hn0lqf//hFsRP2FDXsewib X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260701_061121_470538_FB37C934 X-CRM114-Status: GOOD ( 17.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series is a continuation by AngeloGioacchino Del Regno and I of a previous series ([1]), that adds the clock controller support for the Mediatek MT8189 SoC and its variants (MT8371, MT8391). The first major changes is the split of the series in two: - one for all basic clock controllers including system ones (this series) - one for the multimedia and graphics related clock controllers (to be send in the future) We chose to separate the multimedia clock drivers from the base system ones, as there is currently an unsolvable inter-dependency between the power domains and multimedia clocks; the power domains need a dual-stage bring-up, where only a part of the multimedia clocks are accessible in the first power domain powerup stage, and the rest when the second stage (SRAM enablement) is done. The current workarounds for this issue, such as removing the is_enabled operation from the impacted clock controllers clk_ops table or let the multimedia power domain always on, were quickly discarded for upstream. The second major change is the dt-bindings patch that got heavily reworked, not only because of the split choice. We took the opportunity to regroup in the MT8186 clock and system clock dt-bindings the description of several other Mediatek SoC (MT8188, MT8192 and MT8195) and add in them the MT8189 new ones. The rationale is to ease maintainability and have common files for several currently supported SoC or new future ones, that have the same kind of clock controller design. Finally the pending remarks from peer reviews on the v6 revision of [1] were also taken into account and new fixes and cleanups were also added. A more detailed changelog between [1] and this series: - Removed multimedia and graphics related clock controllers code and definitions from series - Added new dt-bindings patches to factorise existing MT8188, MT8192 and MT8195 in MT8186 clock dt-bindings - Heavily modified the MT8189 dt-bindings to add new compatibles in MT8186 clock dt-bindings - Created a new dt-bindings include for the MT8189 reset controller definitions (include/dt-bindings/reset/mediatek,mt8189-resets.h) - Removed unnecessary `syscon` compatible fallback from MT8189 base clock controllers - Added missing 'mediatek,mt8189-fhctl' compatible declaration in dt-bindings - Modified Kconfig to COMMON_CLK_MT8189 be tristate (and not bool) to allow all MT8189 clock controller drivers to be built as modules (it was partial) - Fix pll unregisters in clk_mt8189_apmixed_probe error case - Reparent several clocks to correct 26M references in clk-mt8189-bus.c, clk-mt8189-topckgen.c and clk-mt8189-vlpckgen.c - Removed CLK_SET_RATE_NO_REPARENT flag from mfg_sel_mfgpll - Rename TOPCKGEN_fmipi_csi_up26m clock to fmipi_csi_up26m to remove caps usage - Implemented reset controllers in clk-mt8189-ufs.c - Updated all file headers to update copyrights and add all authors - Added all co-developed-by trailers The series is based on linux-next tree (tag: next-20260630) and has been tested on Mediatek Genio 520-EVK (MT8371) and 720-EVK (MT8391) boards with board hardware enablement patch series (new series revision for those boards to be sent soon after this one). [1]: https://lore.kernel.org/linux-mediatek/20260309120512.3624804-1-irving-ch.lin@mediatek.com/ [2]: https://lore.kernel.org/linux-mediatek/20260309120512.3624804-2-irving-ch.lin@mediatek.com/ --- Louis-Alexis Eyraud (15): dt-bindings: clock: mediatek: reorder MT8186 compatibles dt-bindings: clock: mediatek: regroup MT8188 dt-bindings into MT8186 dt-bindings: clock: mediatek: regroup MT8192 dt-bindings into MT8186 dt-bindings: clock: mediatek: regroup MT8195 dt-bindings into MT8186 dt-bindings: clock: mediatek: Add MT8189 clocks clk: mediatek: Add MT8189 apmixedsys clock support clk: mediatek: Add MT8189 topckgen clock support clk: mediatek: Add MT8189 vlpckgen clock support clk: mediatek: Add MT8189 vlpcfg clock support clk: mediatek: Add MT8189 bus clock support clk: mediatek: Add MT8189 dbgao clock support clk: mediatek: Add MT8189 dvfsrc clock support clk: mediatek: Add MT8189 i2c clock support clk: mediatek: Add MT8189 scp clock support clk: mediatek: Add MT8189 ufs clock support .../bindings/clock/mediatek,mt8186-clock.yaml | 171 +++- .../bindings/clock/mediatek,mt8186-fhctl.yaml | 1 + .../bindings/clock/mediatek,mt8186-sys-clock.yaml | 42 +- .../bindings/clock/mediatek,mt8188-clock.yaml | 93 -- .../bindings/clock/mediatek,mt8188-sys-clock.yaml | 58 -- .../bindings/clock/mediatek,mt8192-clock.yaml | 191 ---- .../bindings/clock/mediatek,mt8192-sys-clock.yaml | 68 -- .../bindings/clock/mediatek,mt8195-clock.yaml | 238 ----- .../bindings/clock/mediatek,mt8195-sys-clock.yaml | 76 -- drivers/clk/mediatek/Kconfig | 79 ++ drivers/clk/mediatek/Makefile | 8 + drivers/clk/mediatek/clk-mt8189-apmixedsys.c | 196 ++++ drivers/clk/mediatek/clk-mt8189-bus.c | 200 ++++ drivers/clk/mediatek/clk-mt8189-dbgao.c | 98 ++ drivers/clk/mediatek/clk-mt8189-dvfsrc.c | 58 ++ drivers/clk/mediatek/clk-mt8189-iic.c | 122 +++ drivers/clk/mediatek/clk-mt8189-scp.c | 77 ++ drivers/clk/mediatek/clk-mt8189-topckgen.c | 1024 ++++++++++++++++++++ drivers/clk/mediatek/clk-mt8189-ufs.c | 133 +++ drivers/clk/mediatek/clk-mt8189-vlpcfg.c | 115 +++ drivers/clk/mediatek/clk-mt8189-vlpckgen.c | 284 ++++++ include/dt-bindings/clock/mediatek,mt8189-clk.h | 433 +++++++++ include/dt-bindings/reset/mediatek,mt8189-resets.h | 17 + 23 files changed, 3046 insertions(+), 736 deletions(-) --- base-commit: ba7c57499e5999aeae8dd4f954eb2600589d80aa change-id: 20260630-mt8189-clocks-system-base-70714e4ff2aa Best regards, -- Louis-Alexis Eyraud