From: Jie Gan <jie.gan@oss.qualcomm.com>
To: Suzuki K Poulose <suzuki.poulose@arm.com>,
Mike Leach <mike.leach@arm.com>,
James Clark <james.clark@linaro.org>, Leo Yan <leo.yan@arm.com>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Anshuman Khandual <anshuman.khandual@arm.com>,
Yeoreum Yun <yeoreum.yun@arm.com>,
Yuanfang Zhang <yuanfang.zhang@oss.qualcomm.com>,
Maxime Coquelin <mcoquelin.stm32@gmail.com>,
Alexandre Torgue <alexandre.torgue@foss.st.com>,
Tingwei Zhang <tingwei.zhang@oss.qualcomm.com>
Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org,
linux-stm32@st-md-mailman.stormreply.com,
Jie Gan <jie.gan@oss.qualcomm.com>
Subject: [PATCH v2 0/2] fix clock refcount imbalance for all Coresight platform drivers
Date: Thu, 02 Jul 2026 16:54:18 +0800 [thread overview]
Message-ID: <20260702-fix-clock-refcount-unbalance-v2-0-2383fbb9952e@oss.qualcomm.com> (raw)
Found a clock imbalance issue when remove the CTCU module.
coresight_get_enable_clocks() enables the programming clock and the
optional AT clock through devm_clk_get_optional_enabled(), which also
registers a devm action to call clk_disable_unprepare() when the driver
detaches.
After probe, pm_runtime_put() allows the device to suspend and the
runtime suspend callback disables the same clocks. During remove the
device is left runtime suspended, so pm_runtime_disable() freezes it
with the clocks already disabled. The devm cleanup that runs afterwards
calls clk_disable_unprepare() a second time, underflowing the clock
enable refcount.
Resume the device with pm_runtime_get_sync() before tearing it down so
the clocks are enabled again and balance the devm-managed disable. Then
pm_runtime_set_suspended() and pm_runtime_put_noidle() leave the device
in a coherent runtime PM state (suspended, usage count balanced) once
the devm action has disabled the clocks.
Calltrace:
[ 194.074015] ------------[ cut here ]------------
[ 194.078779] qdss already disabled
[ 194.082210] WARNING: drivers/clk/clk.c:1188 at clk_core_disable+0x238/0x240, CPU#4: rmmod/508
[ 194.090976] Modules linked in: coresight_ctcu(-) snd_soc_hdmi_codec snd_soc_core snd_compress snd_pcm_dmaengine snd_pcm snd_timer snd soundcore 8021q garp mrp phy_qcom_edp stp af_alg llc anx7625 typec pci_pwrctrl_pwrseq hci_uart qcom_iris v4l2_mem2mem btqca btbcm qcom_pon videobuf2_dma_contig rtc_pm8xxx nvmem_qcom_spmi_sdam qcom_spmi_temp_alarm videobuf2_memops qrtr videobuf2_v4l2 bluetooth msm qcom_stats pwrseq_qcom_wcn ubwc_config videodev ocmem ecdh_generic drm_gpuvm videobuf2_common drm_exec gpu_sched qcom_q6v5_pas kpp marvell videocc_sa8775p camcc_sa8775p ecc drm_dp_aux_bus dispcc0_sa8775p spi_geni_qcom i2c_qcom_geni llcc_qcom mc qcom_refgen_regulator phy_qcom_snps_femto_v2 phy_qcom_qmp_usb icc_bwmon phy_qcom_sgmii_eth dwmac_qcom_ethqos qcom_pil_info gpucc_sa8775p qcom_q6v5 stmmac_platform stmmac ufs_qcom qcom_sysmon drm_display_helper qcom_common pcs_xpcs phylink cec qcom_glink_smem qcrypto drm_client_lib mdt_loader dispcc1_sa8775p qmi_helpers phy_qcom_qmp_ufs libdes qcom_ice display_connector phy_qcom_qmp_pcie
[ 194.091130] qcom_wdt qcomtee nvmem_reboot_mode icc_osm_l3 qcom_rng drm_kms_helper cfg80211 rfkill socinfo fuse drm backlight stm_p_basic
[ 194.196124] CPU: 4 UID: 0 PID: 508 Comm: rmmod Not tainted 7.1.0-next-20260623-00008-ga4671328ba36 #831 PREEMPT
[ 194.206566] Hardware name: Qualcomm SA8775P Ride (DT)
[ 194.211771] pstate: 604000c5 (nZCv daIF +PAN -UAO -TCO -DIT -SSBS BTYPE=--)
[ 194.218938] pc : clk_core_disable+0x238/0x240
[ 194.223426] lr : clk_core_disable+0x238/0x240
[ 194.227908] sp : ffff8000889fbb40
[ 194.231327] x29: ffff8000889fbb40 x28: ffff0000972eb580 x27: 0000000000000000
[ 194.238662] x26: 0000000000000000 x25: 0000000000000000 x24: 0000000000000000
[ 194.245995] x23: ffffd181d3de4620 x22: ffff8000889fbc28 x21: ffff000082382810
[ 194.253322] x20: ffff000082334a00 x19: ffff000082334a00 x18: 0000000000000006
[ 194.260658] x17: ffffd181d293fb18 x16: ffffd181d295c3c8 x15: ffff8000889fb550
[ 194.267991] x14: 0000000000000000 x13: ffffd181d4eea620 x12: 00000000000004cf
[ 194.275346] x11: 0000000000000e6d x10: ffffd181d4f42620 x9 : ffffd181d4eea620
[ 194.282676] x8 : 3fffffffffffefff x7 : ffffd181d4f42620 x6 : bffffffffffff000
[ 194.290007] x5 : ffff000ead974248 x4 : 0000000000000000 x3 : ffff2e8cd9611000
[ 194.297338] x2 : 0000000000000000 x1 : 0000000000000000 x0 : ffff0000972eb580
[ 194.304671] Call trace:
[ 194.307199] clk_core_disable+0x238/0x240 (P)
[ 194.311687] clk_disable+0x30/0x4c
[ 194.315192] clk_disable_unprepare+0x18/0x30
[ 194.319596] devm_clk_release+0x24/0x3c
[ 194.323578] dr_node_release+0x1c/0x28
[ 194.327466] release_nodes+0x5c/0x90
[ 194.331147] devres_release_all+0x90/0x104
[ 194.335364] device_unbind_cleanup+0x2c/0x84
[ 194.339762] device_release_driver_internal+0x200/0x23c
[ 194.345153] driver_detach+0x4c/0x94
[ 194.348835] bus_remove_driver+0x6c/0xbc
[ 194.352872] driver_unregister+0x30/0x60
[ 194.356914] platform_driver_unregister+0x14/0x20
[ 194.361753] ctcu_driver_exit+0x18/0xdf8 [coresight_ctcu]
[ 194.367308] __arm64_sys_delete_module+0x1bc/0x298
[ 194.372240] invoke_syscall+0x54/0x10c
[ 194.376114] el0_svc_common.constprop.0+0xc0/0xe0
[ 194.380956] do_el0_svc+0x1c/0x28
[ 194.384374] el0_svc+0x54/0x3a0
[ 194.387626] el0t_64_sync_handler+0xa0/0xe4
[ 194.391951] el0t_64_sync+0x198/0x19c
Signed-off-by: Jie Gan <jie.gan@oss.qualcomm.com>
---
Changes in v2:
- Balance the runtime PM state in the remove path: after
pm_runtime_get_sync() and pm_runtime_disable(), also call
pm_runtime_set_suspended() and pm_runtime_put_noidle() so the device is
left suspended with a balanced usage count once the devm action has
disabled the clocks.
- Picked up Reviewed-by from Yeoreum Yun on patch 1.
- Link to v1: https://lore.kernel.org/r/20260701-fix-clock-refcount-unbalance-v1-0-321dc63c1f90@oss.qualcomm.com
---
Jie Gan (2):
coresight: Fix clock refcount imbalance on platform remove
coresight: tnoc: Fix clock refcount imbalance on platform remove
drivers/hwtracing/coresight/coresight-catu.c | 8 ++++++++
drivers/hwtracing/coresight/coresight-cpu-debug.c | 8 ++++++++
drivers/hwtracing/coresight/coresight-ctcu-core.c | 8 ++++++++
drivers/hwtracing/coresight/coresight-etm4x-core.c | 8 ++++++++
drivers/hwtracing/coresight/coresight-funnel.c | 8 ++++++++
drivers/hwtracing/coresight/coresight-replicator.c | 8 ++++++++
drivers/hwtracing/coresight/coresight-stm.c | 8 ++++++++
drivers/hwtracing/coresight/coresight-tmc-core.c | 8 ++++++++
drivers/hwtracing/coresight/coresight-tnoc.c | 8 ++++++++
drivers/hwtracing/coresight/coresight-tpiu.c | 8 ++++++++
10 files changed, 80 insertions(+)
---
base-commit: be5c93fa674f0fc3c8f359c2143abce6bbb422e6
change-id: 20260701-fix-clock-refcount-unbalance-e7c467136a86
Best regards,
--
Jie Gan <jie.gan@oss.qualcomm.com>
next reply other threads:[~2026-07-02 8:54 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-02 8:54 Jie Gan [this message]
2026-07-02 8:54 ` [PATCH v2 1/2] coresight: Fix clock refcount imbalance on platform remove Jie Gan
2026-07-09 15:24 ` Leo Yan
2026-07-10 8:03 ` Jie Gan
2026-07-02 8:54 ` [PATCH v2 2/2] coresight: tnoc: " Jie Gan
2026-07-09 15:27 ` Leo Yan
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