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[47.54.130.67]) by smtp.gmail.com with ESMTPSA id af79cd13be357-92e90ccdf8dsm225956185a.37.2026.07.03.12.24.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 03 Jul 2026 12:25:00 -0700 (PDT) Received: from jgg by wakko with local (Exim 4.97) (envelope-from ) id 1wfjVT-00000008UHZ-0qcN; Fri, 03 Jul 2026 16:24:59 -0300 Date: Fri, 3 Jul 2026 16:24:59 -0300 From: Jason Gunthorpe To: Robin Murphy Cc: will@kernel.org, joro@8bytes.org, jpb@kernel.org, catalin.marinas@arm.com, yangyicong@hisilicon.com, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev, stable@vger.kernel.org Subject: Re: [PATCH] iommu/arm-smmu-v3: Add HAFT support for SVA Message-ID: <20260703192459.GB1978949@ziepe.ca> References: <878cd6bcbbe2d5677d2f63da13294c148268552c.1782927917.git.robin.murphy@arm.com> <20260703164914.GY7525@ziepe.ca> <6465c885-3a9d-4c0b-ab74-7665e274ae72@arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <6465c885-3a9d-4c0b-ab74-7665e274ae72@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260703_122502_618918_EE10D50B X-CRM114-Status: GOOD ( 27.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 03, 2026 at 07:57:04PM +0100, Robin Murphy wrote: > On 03/07/2026 5:49 pm, Jason Gunthorpe wrote: > > On Wed, Jul 01, 2026 at 06:45:17PM +0100, Robin Murphy wrote: > > > > > @@ -211,6 +213,9 @@ bool arm_smmu_sva_supported(struct arm_smmu_device *smmu) > > > if (system_supports_bbml2_noabort()) > > > feat_mask |= ARM_SMMU_FEAT_BBML2; > > > + if (system_supports_haft()) > > > + feat_mask |= ARM_SMMU_FEAT_HAFT; > > > > I fear this is going to make SVA stop working on systems it currently > > does work on, so it might be a major regression. > > > > SMMU HTTU is not a commonly implemented feature.. I think of all the > > NVIDIA ARM chips only one supports it. Given that a quick internal > > check is raising concerns this will be breaking for us. We need to > > check in more detail which cores have HAFT. > > > > Breaking already deployed SVA would be a major functional regression. > > > > I think this should start by just enabling SMMU HAFT when CPU HAFT is > > on, when possible. Maybe print a warning on the mismatch instead of > > failing. > > > > Since we can't break already deployed SVA a full solution would either > > have to somehow turn off CPU HAFT or we ignore the gap in the AF > > updates.. > > TBH I do not know how bad the implications of > pmd_young()/pmdp_test_and_clear_young() returning a false-negative are, but > if we aren't considering mismatched CPUs harmless then surely the same must > apply for SVA. In the POE/GCS cases all that can really be broken is users' > expectations, if they've opted in to additional security features, but also > opted in to SVA wherein those features can't protect against DMA. Here, > though, it's the kernel mm layer itself that's impacted, and I'm not > confident to say that that isn't more serious. This has come up a few times now where the SMMU and CPU incompatibilities in ARM's IP are causing real headaches. Let's give it some time and I can say for certain if we have impacted chips or not. I was able to confirm the server chips are OK, but there is still some concern about the embedded chips.. I also don't know how harmless it is to ignore the aging. I thought the PTE was designed to be backwards compatible, but I never looked at how AF works.. > Making HAFT depend on !SVA could only easily be done at the config > level, which seems arguably even more over-reaching Yeah, but if you could build a custom embedded kernel with HAFT disabled in kconfig maybe that is enough for some people. Jason