From: Krzysztof Kozlowski <krzk@kernel.org>
To: Paul Louvel <paul.louvel@bootlin.com>
Cc: Qiang Zhao <qiang.zhao@nxp.com>,
"Christophe Leroy (CS GROUP)" <chleroy@kernel.org>,
Thomas Gleixner <tglx@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>,
Madhavan Srinivasan <maddy@linux.ibm.com>,
Michael Ellerman <mpe@ellerman.id.au>,
Nicholas Piggin <npiggin@gmail.com>,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, devicetree@vger.kernel.org,
linux-gpio@vger.kernel.org,
Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Subject: Re: [PATCH 04/12] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO
Date: Mon, 6 Jul 2026 08:52:51 +0200 [thread overview]
Message-ID: <20260706-elfish-cornflower-bullfinch-604e0a@quoll> (raw)
In-Reply-To: <20260703-qe-pic-gpios-v1-4-6c3e706e27dc@bootlin.com>
On Fri, Jul 03, 2026 at 03:30:12PM +0200, Paul Louvel wrote:
> Some QE GPIO pins have an associated interrupt line in the QE PIC to
> signal state changes on the pin. Add the corresponding
> interrupt-controller / nexus properties to the QE GPIO binding.
>
> Because the GPIO controller does not perform any interrupt handling
> itself, a nexus node (interrupt-map) is used to map each GPIO line
> supporting IRQ to the parent QE PIC interrupt domain.
>
> As the QE PIC can be configured to generate an interrupt on either a
> high-to-low transition or any change in signal state, three
> interrupt-map entries are needed per GPIO pin that can yield an
> interrupt (falling, both, and the "none" case which defaults to both in
> QE PIC). This overhead is necessary because the interrupt-map-pass-thru
> property is not part of the DT specification.
>
> The interrupt-map property is optional: it is not required for GPIO
> banks that have no interrupt capable GPIO line (e.g. port D on MPC8323),
> or when interrupt functionality is not used.
>
> Update the example to show a scenario where each bank supports a
> different numbers of IRQs, or no IRQs at all.
>
> Signed-off-by: Paul Louvel <paul.louvel@bootlin.com>
> ---
> .../bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml | 69 +++++++++++++++++++++-
> 1 file changed, 66 insertions(+), 3 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml b/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml
> index 1af99339ff40..0c849a5698f4 100644
> --- a/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml
> +++ b/Documentation/devicetree/bindings/gpio/fsl,mpc8323-qe-pario-bank.yaml
> @@ -27,6 +27,17 @@ properties:
> "#gpio-cells":
> const: 2
>
> + "#address-cells":
> + const: 0
> +
> + "#interrupt-cells":
> + const: 2
> +
If this has interrupt-cells, then it is a nexus, thus why isn't this
also a "interrupt-controller"?
> + interrupt-map:
> + description: |
> + Specifies the mapping of GPIO lines to the parent interrupt controller, as the
> + GPIO controller does not do interrupt handling itself.
> +
> required:
> - compatible
> - reg
> @@ -37,9 +48,61 @@ additionalProperties: false
>
> examples:
> - |
> - gpio-controller@1400 {
> - compatible = "fsl,mpc8360-qe-pario-bank", "fsl,mpc8323-qe-pario-bank";
> - reg = <0x1400 0x18>;
I don't get why you rewrite existing example instead of adding new one.
> + #include <dt-bindings/interrupt-controller/irq.h>
> +
> + pic: interrupt-controller {
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + };
Drop node, irrelevant.
> +
> + gpio-controller@1418 {
> + #gpio-cells = <2>;
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + compatible = "fsl,mpc8323-qe-pario-bank";
> + reg = <0x1418 0x18>;
And now you are not following DTS coding style.
> gpio-controller;
> + interrupt-map = <
> + 7 IRQ_TYPE_EDGE_FALLING &pic 4 IRQ_TYPE_EDGE_FALLING
> + 7 IRQ_TYPE_EDGE_BOTH &pic 4 IRQ_TYPE_EDGE_BOTH
> + 7 0 &pic 4 IRQ_TYPE_NONE
> +
> + 9 IRQ_TYPE_EDGE_FALLING &pic 5 IRQ_TYPE_EDGE_FALLING
> + 9 IRQ_TYPE_EDGE_BOTH &pic 5 IRQ_TYPE_EDGE_BOTH
> + 9 0 &pic 5 IRQ_TYPE_NONE
> +
> + 25 IRQ_TYPE_EDGE_FALLING &pic 6 IRQ_TYPE_EDGE_FALLING
> + 25 IRQ_TYPE_EDGE_BOTH &pic 6 IRQ_TYPE_EDGE_BOTH
> + 25 0 &pic 6 IRQ_TYPE_NONE
> +
> + 27 IRQ_TYPE_EDGE_FALLING &pic 7 IRQ_TYPE_EDGE_FALLING
> + 27 IRQ_TYPE_EDGE_BOTH &pic 7 IRQ_TYPE_EDGE_BOTH
> + 27 0 &pic 7 IRQ_TYPE_NONE
> + >;
> + };
> +
> + gpio-controller@1430 {
> #gpio-cells = <2>;
So two new examples? But old one was wrong?
> + #address-cells = <0>;
> + #interrupt-cells = <2>;
> + compatible = "fsl,mpc8323-qe-pario-bank";
> + reg = <0x1430 0x18>;
> + gpio-controller;
> + interrupt-map = <
> + 24 IRQ_TYPE_EDGE_FALLING &pic 8 IRQ_TYPE_EDGE_FALLING
> + 24 IRQ_TYPE_EDGE_BOTH &pic 8 IRQ_TYPE_EDGE_BOTH
> + 24 0 &pic 8 IRQ_TYPE_NONE
> +
> + 29 IRQ_TYPE_EDGE_FALLING &pic 9 IRQ_TYPE_EDGE_FALLING
> + 29 IRQ_TYPE_EDGE_BOTH &pic 9 IRQ_TYPE_EDGE_BOTH
> + 29 0 &pic 9 IRQ_TYPE_NONE
> + >;
> + };
> +
> + gpio-controller@1448 {
> + #gpio-cells = <2>;
> + compatible = "fsl,mpc8323-qe-pario-bank";
Wait, three examples? But isn't this the same as previous one?
> + reg = <0x1448 0x18>;
> + gpio-controller;
> };
>
> --
> 2.55.0
>
next prev parent reply other threads:[~2026-07-06 6:53 UTC|newest]
Thread overview: 19+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-03 13:30 [PATCH 00/12] soc: fsl: qe: QE PIC improvement and add support of IRQs to QUICC ENGINE GPIOs Paul Louvel
2026-07-03 13:30 ` [PATCH 01/12] soc: fsl: qe: Add chained_irq_{enter,exit}() calls in cascade handler Paul Louvel
2026-07-03 13:30 ` [PATCH 02/12] dt-bindings: soc: fsl: qe: Set #interrupt-cells to 2 to support interrupt type encoding Paul Louvel
2026-07-03 13:30 ` [PATCH 03/12] dt-bindings: soc: fsl: qe: Convert QE GPIO to DT schema Paul Louvel
2026-07-06 6:48 ` Krzysztof Kozlowski
2026-07-06 9:03 ` Paul Louvel
2026-07-03 13:30 ` [PATCH 04/12] dt-bindings: soc: fsl: qe: Add support of IRQ in QE GPIO Paul Louvel
2026-07-06 6:52 ` Krzysztof Kozlowski [this message]
2026-07-06 8:48 ` Paul Louvel
2026-07-03 13:30 ` [PATCH 05/12] soc: fsl: qe: Use generic_handle_domain_irq() Paul Louvel
2026-07-03 13:30 ` [PATCH 06/12] soc: fsl: qe: Iterate over all pending interrupts in cascade handler Paul Louvel
2026-07-03 13:30 ` [PATCH 07/12] soc: fsl: qe: Handle spurious interrupts Paul Louvel
2026-07-03 13:30 ` [PATCH 08/12] soc: fsl: qe: Convert to generic IRQ chip Paul Louvel
2026-07-06 7:29 ` Christophe Leroy (CS GROUP)
2026-07-06 8:56 ` Paul Louvel
2026-07-03 13:30 ` [PATCH 09/12] soc: fsl: qe: Rename irq variable to parent_irq Paul Louvel
2026-07-03 13:30 ` [PATCH 10/12] soc: fsl: qe: Rename host member to domain in struct qepic_data Paul Louvel
2026-07-03 13:30 ` [PATCH 11/12] soc: fsl: qe: Remove useless struct member Paul Louvel
2026-07-03 13:30 ` [PATCH 12/12] soc: fsl: qe: Add support of IRQs in QE GPIO Paul Louvel
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