From: Simon Glass <sjg@chromium.org>
To: Heiko Stuebner <heiko@sntech.de>
Cc: linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org,
Fabio Estevam <festevam@nabladev.com>,
linux-arm-kernel@lists.infradead.org,
Simon Glass <sjg@chromium.org>,
Jeffy Chen <jeffy.chen@rock-chips.com>,
Linus Walleij <linusw@kernel.org>, huang lin <hl@rock-chips.com>,
linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: [PATCH 04/12] pinctrl: rockchip: Add RV1106 pinctrl support
Date: Mon, 6 Jul 2026 13:58:00 -0600 [thread overview]
Message-ID: <20260706195818.3906949-5-sjg@chromium.org> (raw)
In-Reply-To: <20260706195818.3906949-1-sjg@chromium.org>
Add pinctrl support for the Rockchip RV1106, taken from the vendor
kernel in the Luckfox Pico SDK [1] at commit 824b817f8 (a Linux
5.10.160 kernel tree). The IOC registers are spread across several
blocks, addressed through per-bank offsets, with the GPIO0 block in the
PMU. The drive strength uses the RK3568-style exponential encoding.
The RV1103 is a package variant of the RV1106 with fewer pins and uses
the same pin controller.
[1] https://github.com/LuckfoxTECH/luckfox-pico
Signed-off-by: Simon Glass <sjg@chromium.org>
---
drivers/pinctrl/pinctrl-rockchip.c | 208 +++++++++++++++++++++++++++++
drivers/pinctrl/pinctrl-rockchip.h | 1 +
2 files changed, 209 insertions(+)
diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c
index 7e0fcd45fd26..f9cbcb955853 100644
--- a/drivers/pinctrl/pinctrl-rockchip.c
+++ b/drivers/pinctrl/pinctrl-rockchip.c
@@ -1725,6 +1725,166 @@ static int rv1103b_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
return 0;
}
+#define RV1106_DRV_BITS_PER_PIN 8
+#define RV1106_DRV_PINS_PER_REG 2
+#define RV1106_DRV_GPIO0_OFFSET 0x10
+#define RV1106_DRV_GPIO1_OFFSET 0x80
+#define RV1106_DRV_GPIO2_OFFSET 0x100C0
+#define RV1106_DRV_GPIO3_OFFSET 0x20100
+#define RV1106_DRV_GPIO4_OFFSET 0x30020
+
+static int rv1106_calc_drv_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* GPIO0_IOC is located in PMU */
+ switch (bank->bank_num) {
+ case 0:
+ *regmap = info->regmap_pmu;
+ *reg = RV1106_DRV_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *regmap = info->regmap_base;
+ *reg = RV1106_DRV_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *regmap = info->regmap_base;
+ *reg = RV1106_DRV_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *regmap = info->regmap_base;
+ *reg = RV1106_DRV_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *regmap = info->regmap_base;
+ *reg = RV1106_DRV_GPIO4_OFFSET;
+ break;
+
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RV1106_DRV_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1106_DRV_PINS_PER_REG;
+ *bit *= RV1106_DRV_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RV1106_PULL_BITS_PER_PIN 2
+#define RV1106_PULL_PINS_PER_REG 8
+#define RV1106_PULL_GPIO0_OFFSET 0x38
+#define RV1106_PULL_GPIO1_OFFSET 0x1C0
+#define RV1106_PULL_GPIO2_OFFSET 0x101D0
+#define RV1106_PULL_GPIO3_OFFSET 0x201E0
+#define RV1106_PULL_GPIO4_OFFSET 0x30070
+
+static int rv1106_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num, struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* GPIO0_IOC is located in PMU */
+ switch (bank->bank_num) {
+ case 0:
+ *regmap = info->regmap_pmu;
+ *reg = RV1106_PULL_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *regmap = info->regmap_base;
+ *reg = RV1106_PULL_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *regmap = info->regmap_base;
+ *reg = RV1106_PULL_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *regmap = info->regmap_base;
+ *reg = RV1106_PULL_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *regmap = info->regmap_base;
+ *reg = RV1106_PULL_GPIO4_OFFSET;
+ break;
+
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RV1106_PULL_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1106_PULL_PINS_PER_REG;
+ *bit *= RV1106_PULL_BITS_PER_PIN;
+
+ return 0;
+}
+
+#define RV1106_SMT_BITS_PER_PIN 1
+#define RV1106_SMT_PINS_PER_REG 8
+#define RV1106_SMT_GPIO0_OFFSET 0x40
+#define RV1106_SMT_GPIO1_OFFSET 0x280
+#define RV1106_SMT_GPIO2_OFFSET 0x10290
+#define RV1106_SMT_GPIO3_OFFSET 0x202A0
+#define RV1106_SMT_GPIO4_OFFSET 0x300A0
+
+static int rv1106_calc_schmitt_reg_and_bit(struct rockchip_pin_bank *bank,
+ int pin_num,
+ struct regmap **regmap,
+ int *reg, u8 *bit)
+{
+ struct rockchip_pinctrl *info = bank->drvdata;
+
+ /* GPIO0_IOC is located in PMU */
+ switch (bank->bank_num) {
+ case 0:
+ *regmap = info->regmap_pmu;
+ *reg = RV1106_SMT_GPIO0_OFFSET;
+ break;
+
+ case 1:
+ *regmap = info->regmap_base;
+ *reg = RV1106_SMT_GPIO1_OFFSET;
+ break;
+
+ case 2:
+ *regmap = info->regmap_base;
+ *reg = RV1106_SMT_GPIO2_OFFSET;
+ break;
+
+ case 3:
+ *regmap = info->regmap_base;
+ *reg = RV1106_SMT_GPIO3_OFFSET;
+ break;
+
+ case 4:
+ *regmap = info->regmap_base;
+ *reg = RV1106_SMT_GPIO4_OFFSET;
+ break;
+
+ default:
+ dev_err(info->dev, "unsupported bank_num %d\n", bank->bank_num);
+ break;
+ }
+
+ *reg += ((pin_num / RV1106_SMT_PINS_PER_REG) * 4);
+ *bit = pin_num % RV1106_SMT_PINS_PER_REG;
+ *bit *= RV1106_SMT_BITS_PER_PIN;
+
+ return 0;
+}
+
#define RV1108_PULL_PMU_OFFSET 0x10
#define RV1108_PULL_OFFSET 0x110
#define RV1108_PULL_PINS_PER_REG 8
@@ -3310,6 +3470,7 @@ static int rockchip_set_drive_perpin(struct rockchip_pin_bank *bank,
ret = strength;
goto config;
} else if (ctrl->type == RV1103B ||
+ ctrl->type == RV1106 ||
ctrl->type == RK3506 ||
ctrl->type == RK3528 ||
ctrl->type == RK3562 ||
@@ -3482,6 +3643,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num)
: PIN_CONFIG_BIAS_DISABLE;
case PX30:
case RV1103B:
+ case RV1106:
case RV1108:
case RK3188:
case RK3288:
@@ -3547,6 +3709,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank,
break;
case PX30:
case RV1103B:
+ case RV1106:
case RV1108:
case RV1126:
case RK3188:
@@ -3843,6 +4006,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl,
return pull ? false : true;
case PX30:
case RV1103B:
+ case RV1106:
case RV1108:
case RV1126:
case RK3188:
@@ -4623,6 +4787,48 @@ static struct rockchip_pin_ctrl rv1103b_pin_ctrl __maybe_unused = {
.schmitt_calc_reg = rv1103b_calc_schmitt_reg_and_bit,
};
+static struct rockchip_pin_bank rv1106_pin_banks[] = {
+ PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0",
+ IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU,
+ IOMUX_WIDTH_4BIT | IOMUX_SOURCE_PMU),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(1, 32, "gpio1",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0, 0x08, 0x10, 0x18),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(2, 32, "gpio2",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x10020, 0x10028, 0, 0),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(3, 32, "gpio3",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0x20040, 0x20048, 0x20050, 0x20058),
+ PIN_BANK_IOMUX_FLAGS_OFFSET(4, 24, "gpio4",
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ IOMUX_WIDTH_4BIT,
+ 0,
+ 0x30000, 0x30008, 0x30010, 0),
+};
+
+static struct rockchip_pin_ctrl rv1106_pin_ctrl __maybe_unused = {
+ .pin_banks = rv1106_pin_banks,
+ .nr_banks = ARRAY_SIZE(rv1106_pin_banks),
+ .label = "RV1106-GPIO",
+ .type = RV1106,
+ .pull_calc_reg = rv1106_calc_pull_reg_and_bit,
+ .drv_calc_reg = rv1106_calc_drv_reg_and_bit,
+ .schmitt_calc_reg = rv1106_calc_schmitt_reg_and_bit,
+};
+
static struct rockchip_pin_bank rv1108_pin_banks[] = {
PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_SOURCE_PMU,
IOMUX_SOURCE_PMU,
@@ -5261,6 +5467,8 @@ static const struct of_device_id rockchip_pinctrl_dt_match[] = {
.data = &px30_pin_ctrl },
{ .compatible = "rockchip,rv1103b-pinctrl",
.data = &rv1103b_pin_ctrl },
+ { .compatible = "rockchip,rv1106-pinctrl",
+ .data = &rv1106_pin_ctrl },
{ .compatible = "rockchip,rv1108-pinctrl",
.data = &rv1108_pin_ctrl },
{ .compatible = "rockchip,rv1126-pinctrl",
diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h
index bb0e803e3b8a..e8b5e850bbef 100644
--- a/drivers/pinctrl/pinctrl-rockchip.h
+++ b/drivers/pinctrl/pinctrl-rockchip.h
@@ -186,6 +186,7 @@
enum rockchip_pinctrl_type {
PX30,
RV1103B,
+ RV1106,
RV1108,
RV1126,
RK2928,
--
2.43.0
next prev parent reply other threads:[~2026-07-06 19:59 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-07-06 19:57 [PATCH 00/12] Add support for the Rockchip RV1106 and RV1103 Simon Glass
2026-07-06 19:57 ` [PATCH 01/12] dt-bindings: clock: rockchip: Add RV1106 CRU support Simon Glass
2026-07-06 19:57 ` [PATCH 02/12] clk: rockchip: Add clock controller for the RV1106 Simon Glass
2026-07-06 19:57 ` [PATCH 03/12] dt-bindings: pinctrl: rockchip: Add RV1106 compatible Simon Glass
2026-07-06 19:58 ` Simon Glass [this message]
2026-07-06 19:58 ` [PATCH 05/12] dt-bindings: soc: rockchip: grf: Add RV1106 compatibles Simon Glass
2026-07-06 19:58 ` [PATCH 06/12] dt-bindings: serial: snps-dw-apb-uart: Add RV1106 compatible Simon Glass
2026-07-06 19:58 ` [PATCH 07/12] dt-bindings: mmc: rockchip-dw-mshc: " Simon Glass
2026-07-06 19:58 ` [PATCH 08/12] dt-bindings: watchdog: snps,dw-wdt: " Simon Glass
2026-07-06 19:58 ` [PATCH 09/12] dt-bindings: iio: adc: rockchip-saradc: " Simon Glass
2026-07-07 2:09 ` Jonathan Cameron
2026-07-06 19:58 ` [PATCH 10/12] ARM: dts: rockchip: Add support for RV1106 and RV1103 Simon Glass
2026-07-06 19:58 ` [PATCH 11/12] dt-bindings: arm: rockchip: Add Luckfox Pico Mini B Simon Glass
2026-07-06 19:58 ` [PATCH 12/12] ARM: dts: " Simon Glass
2026-07-06 22:54 ` [PATCH 00/12] Add support for the Rockchip RV1106 and RV1103 Fabio Estevam
2026-07-07 7:41 ` Heiko Stübner
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