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bh=xfccldLVCxkbEtlVItFgKJxpZCQLxtTCzIH5oBIqVAM=; b=HciGiTdGX0B4YjvdZOHv6vtUEhYWXigGBFKcFX2uE8+b39utoCSA8Ct1P2KyRaIU05rSQq 9OfMIZjQptVYSf7HSEt56HlND0Mtc4eA75yMW99Rw65TucrfAiiIZLIvmHfET1MYlUUc0P ps5+b5EYZvHZph8rNbE0kVjn8aMeYY4KYPrVKnoDbIUq6mzsYnl49shAxNPjuR6Pgh4pyM x+yr1V0KmulirhafauMAaZAsnRanNjnkqn1ARvA8DOMCSMMhtFdeRnYJRAZ02yFFDblvTc HE+UMp88BZ3L9PabznZCUMlB2KnmxKEGXONwmbhLlQ8ZfFP8IqWW7PuLWWxLRw== Authentication-Results: outgoing_mbo_mout; dkim=pass header.d=mailbox.org header.s=mail20150812 header.b=P0opyTmz; spf=pass (outgoing_mbo_mout: domain of marek.vasut+renesas@mailbox.org designates 2001:67c:2050:b231:465::202 as permitted sender) smtp.mailfrom=marek.vasut+renesas@mailbox.org From: Marek Vasut DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=mailbox.org; s=mail20150812; t=1783456696; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xfccldLVCxkbEtlVItFgKJxpZCQLxtTCzIH5oBIqVAM=; b=P0opyTmz2tfP23EpSSkte30I85hZ6Fr3d3HZsnt6Y3CoVRaqcpxEc4pZm7Svzdljp/FLkX mbOOKZF7MpRA1fTDONiCZF8K8qsxgLcmsnvLzepWJsKsOyAkmMDKUKRcpUGfHPe2HpPbyu +FpMg+hAUObutRqu99moHH8mYf+BT8ZrOH/nRi7vDOMX14TuBCUBq6n3TKgk0z8L6feacK zZsNlFt5xqISGIHiCzl1A2Pm16S9qDHKK2KaPxFapLsARBhsU0MFJrq+vDsJx5/eEi/DtK hFgZeI7McPFMhrWYCXW6UTB4NqyZ9iLnTqZGrYyPpAC3rl55A6pO4v3IBzFbhQ== To: linux-pci@vger.kernel.org Cc: Marek Vasut , Yoshihiro Shimoda , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Bjorn Helgaas , Catalin Marinas , Conor Dooley , Geert Uytterhoeven , Krzysztof Kozlowski , Lorenzo Pieralisi , Manivannan Sadhasivam , Marc Zyngier , Rob Herring , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v4 5/5] arm64: dts: renesas: r8a779g0: Add GICv3 ITS and update PCIe nodes Date: Tue, 7 Jul 2026 22:35:43 +0200 Message-ID: <20260707203743.88299-6-marek.vasut+renesas@mailbox.org> In-Reply-To: <20260707203743.88299-1-marek.vasut+renesas@mailbox.org> References: <20260707203743.88299-1-marek.vasut+renesas@mailbox.org> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-MBO-RS-ID: c41e573af602e797cf2 X-MBO-RS-META: ywcwk7y9uqr5xhh5osbrhnjh1p73wr5x X-Rspamd-Queue-Id: 4gvtNB1gDqzKnYq X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260707_133821_079340_E3A42EE5 X-CRM114-Status: GOOD ( 12.54 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This SoC implements GIC600 with GICv3 ITS and PCIe host mode on this SoC can use it. Add GIC ITS node into GIC node, update interrupt-map and add msi-map into PCIe controller node. The GIC ITS does have master interface to issue transactions to RAM. The interface does support cacheable transactions, however, it does not support shareable attribute, because the AXI port signals are tied to inactive in this implementation. Therefore, add "dma-noncoherent" DT property into the GIC ITS subnode. The GIC redistributor does not have cacheable/shareable, therefore add "dma-noncoherent" DT property into the GIC node. Co-developed-by: Yoshihiro Shimoda Signed-off-by: Yoshihiro Shimoda Signed-off-by: Marek Vasut --- NOTE: This would not be possible without prior work from Shimoda-san https://lore.kernel.org/all/20240214052144.1966569-1-yoshihiro.shimoda.uh@renesas.com/ --- Cc: "Krzysztof Wilczyński" Cc: Bjorn Helgaas Cc: Catalin Marinas Cc: Conor Dooley Cc: Geert Uytterhoeven Cc: Krzysztof Kozlowski Cc: Lorenzo Pieralisi Cc: Manivannan Sadhasivam Cc: Marc Zyngier Cc: Rob Herring Cc: Yoshihiro Shimoda Cc: devicetree@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Cc: linux-doc@vger.kernel.org Cc: linux-kernel@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: linux-renesas-soc@vger.kernel.org --- V2: No change V3: Add Co-developed-by to credit Shimoda-san V4: No change --- arch/arm64/boot/dts/renesas/r8a779g0.dtsi | 31 ++++++++++++++++------- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi index c25642a620db8..dba46499b5e9c 100644 --- a/arch/arm64/boot/dts/renesas/r8a779g0.dtsi +++ b/arch/arm64/boot/dts/renesas/r8a779g0.dtsi @@ -809,6 +809,7 @@ pciec0: pcie@e65d0000 { resets = <&cpg 624>; reset-names = "pwr"; max-link-speed = <4>; + msi-parent = <&its>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; @@ -819,10 +820,10 @@ pciec0: pcie@e65d0000 { dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 449 IRQ_TYPE_LEVEL_HIGH>; snps,enable-cdm-check; status = "disabled"; @@ -856,6 +857,7 @@ pciec1: pcie@e65d8000 { resets = <&cpg 625>; reset-names = "pwr"; max-link-speed = <4>; + msi-parent = <&its>; num-lanes = <2>; #address-cells = <3>; #size-cells = <2>; @@ -866,10 +868,10 @@ pciec1: pcie@e65d8000 { dma-ranges = <0x42000000 0 0x00000000 0 0x00000000 1 0x00000000>; #interrupt-cells = <1>; interrupt-map-mask = <0 0 0 7>; - interrupt-map = <0 0 0 1 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 2 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 3 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, - <0 0 0 4 &gic GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; + interrupt-map = <0 0 0 1 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 2 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 3 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>, + <0 0 0 4 &gic 0 0 GIC_SPI 456 IRQ_TYPE_LEVEL_HIGH>; snps,enable-cdm-check; status = "disabled"; @@ -2148,11 +2150,22 @@ ipmmu_mm: iommu@eefc0000 { gic: interrupt-controller@f1000000 { compatible = "arm,gic-v3"; #interrupt-cells = <3>; - #address-cells = <0>; + #address-cells = <2>; + #size-cells = <2>; interrupt-controller; reg = <0x0 0xf1000000 0 0x20000>, <0x0 0xf1060000 0 0x110000>; interrupts = ; + dma-noncoherent; + + ranges = <0x0 0x0 0x0 0xf1000000 0x0 0x200000>; + + its: msi-controller@40000 { + compatible = "arm,gic-v3-its"; + reg = <0x0 0x40000 0x0 0x20000>; + dma-noncoherent; + msi-controller; + }; }; gpu: gpu@fd000000 { -- 2.53.0