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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Suraj Gupta , Marek Vasut , Tomi Valkeinen , Alex Bereza , "Folker Schwesinger" , , , , , Subject: [PATCH V3 0/4] dmaengine: xilinx_dma: MCDMA descriptor and metadata handling improvements Date: Wed, 8 Jul 2026 15:36:48 +0530 Message-ID: <20260708100652.603074-1-srinivas.neeli@amd.com> X-Mailer: git-send-email 2.25.1 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B077:EE_|DM4PR12MB6135:EE_ X-MS-Office365-Filtering-Correlation-Id: 01a5747d-3828-4476-8726-08dedcd8f69e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|82310400026|7416014|376014|36860700016|6133799003|13003099007|18002099003|11063799006|56012099006; X-Microsoft-Antispam-Message-Info: Rxl5xCXdNgqKS6wx8+LAcwQL2WKuZ3B0/6xVDkIHkZDRf6sI560lF4J/eyDwn2qjvFQbKVqtqhosb6jSIhqy434ecOWWDnA1l8ngk8R/1ahupb0NqyjovqG3hTLuIEiisjrEbhit6U0slWHBnI2XoGaG4uQ5vkcnwzCjH9WH8yih7pMgcnWB7l9G+iHJ5LY2i5jMgjBiQl950ZfIZ3vDhl8/YRSgHJ64x40mwzhjs/wmst0cFKGhvjCg9FtpGu9tgKknwXCw6PS8cwXDZIJEnkgHYfBEa80hZ1BdP06sEFKn7b2dv5SQK696mUrNUO2VKvqIbN6OdA+XwAdx4fwn+wRPD3RsejyXmp7tBhubQrL7V6iMT0s7gTAbI8BnlrtIQVycmbqmfscd94P0pz/VTG+rhEF+rIG9jwDIShqw8t7bYHv6NdnfUapdTgjhnHTZ5lNjWSFchxBkzsGAic3cswOjHGkWyGwoIHN330KO7j2wt5LLJ52BHmM82qRi336oeTkggd5YZJNTc1OfP8fh0/Cchcv5h4RU/jXfmyzXkTRM5v0fv3IUM1/Lgvuqc4i3LR4to/vhqIzKTmwkvxNaKf7LM5SwPSrxuJRg+qEiIFgauTJcPbGN06XeV+zE+euER40Ipqpu9kBahb1yph1AhrhcbQqQw+aCZa85STtNW7N1Bcud9okBKR5utRdOoQMADbxZVAejp1KICZBnYdB4xA== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(1800799024)(23010399003)(82310400026)(7416014)(376014)(36860700016)(6133799003)(13003099007)(18002099003)(11063799006)(56012099006);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: Jp/w6coiQMjlsBaL6mp66/V0CE9694wKF52zzgIcFH73Vxecg5vAFhM7+G7iHjSdswnGPwk1F9CdmbOiamHAeL75Z+MQrPRGTIB07W8GcOrccu2vhd83KK9+T5tPAxLLljjSX/hJ1B6xszdAFZNdgBKNtv7H4nS3jE+C5uUFYqcblTLWlCXhrEv27MDi7nCA5gH6p9bFahk6jBHEz4g8HAohaxKH3pTeHIW9VWQgwqNDzRzHYen3yzsVSJnpyZQxCwrJXCqPn4TRuPwQEL0v8of6wFJ8eNg/EE4scHbqBRD0/jeseBZHAgqcHTg5u7FIyNwZxSYhJ5jOYFj94qOruTmSTwrKJVWKSTrhy72UkYi+1Ch4qxv5KZJxW6XaSNJpOPUxbhqvKPeIdpDCW7eNy6OWX9V7IaEUGm4QEg9M84B3lVkTn6Y8gBjQoa9cT1gi X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 08 Jul 2026 10:09:14.1386 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 01a5747d-3828-4476-8726-08dedcd8f69e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B077.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6135 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260708_030924_035678_685854FF X-CRM114-Status: GOOD ( 10.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series improves the Xilinx AXI DMA and MCDMA driver's descriptor handling and metadata reporting. It fixes direction-specific descriptor field usage, ensures completion is based on the hardware completion bit (important with interrupt coalescing), and extends metadata handling to expose status and sideband fields alongside APP fields. The axienet driver is updated to derive RX frame length from the standard dmaengine residue mechanism rather than descriptor APP fields, making it work on designs where the AXI4-Stream status/control interface is not present. Changes in V3: - Patch 1: Renamed subject, added static_assert for descriptor size, refactored residue calculation for clarity. - Patch 2: Added Fixes tag, expanded commit message explaining interrupt coalescing scenario, simplified completion check logic. - Patch 3: New patch - axienet now uses result->residue for RX length instead of APP metadata, removing dependency on status/control stream. - Patch 4: Complete rewrite - metadata pointer now starts at status field (index 0) exposing status/sideband to clients; uses EOF descriptor; removed 'chan' field from descriptor struct. - Dropped V2 patches 4/5 (dt-bindings) and 5/5 (xferred_bytes) as the approach changed to use standard residue mechanism. Changes in V2: - Rebased on the AXI DMA binding YAML conversion. - Added xlnx,include-stscntrl-strm in the YAML binding. - Clarified cover letter to reflect metadata behavior with and without APP fields. https://lore.kernel.org/all/20260309033444.3472359-1-abin.joseph@amd.com/ Srinivas Neeli (3): dmaengine: xilinx_dma: Fix MCDMA descriptor fields based on DMA direction dmaengine: xilinx_dma: Move descriptors to done list based on completion bit net: xilinx: axienet: Derive RX frame length from DMA residue Suraj Gupta (1): dmaengine: xilinx_dma: Extend metadata handling for AXI DMA and MCDMA drivers/dma/xilinx/xilinx_dma.c | 85 ++++++++++++++++--- .../net/ethernet/xilinx/xilinx_axienet_main.c | 14 ++- 2 files changed, 76 insertions(+), 23 deletions(-) -- 2.25.1