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Also add the tuples by pair in example. In static-config mode the IP exposes only fixed-factor clock outputs and has no runtime-programmable registers, so reg is not required. Make reg optional for static-config In static-config mode the AXI bus interface is unused, so s_axi_aclk is not required. Allow clocks/clock-names to have only one entry (clk_in1) when xlnx,static-config is present and enforce two entries otherwise. Update the static-config example accordingly. Signed-off-by: Shubhrajyoti Datta --- Changes in v2: Merged the similar patches Allow check for current dt even if it is unused. .../bindings/clock/xlnx,clocking-wizard.yaml | 53 +++++++++++++++++-- 1 file changed, 48 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml index b497c28e8094..865927b9f1be 100644 --- a/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml +++ b/Documentation/devicetree/bindings/clock/xlnx,clocking-wizard.yaml @@ -29,11 +29,13 @@ properties: const: 1 clocks: + minItems: 1 items: - description: clock input - description: axi clock clock-names: + minItems: 1 items: - const: clk_in1 - const: s_axi_aclk @@ -57,27 +59,68 @@ properties: description: Number of outputs. + xlnx,clk-mul-div: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: + Fixed MMCM/PLL multiply/divide ratios, one (multiplier, divisor) + pair per clock output relative to clk_in1. The number of entries + must equal xlnx,nr-outputs. + minItems: 1 + maxItems: 8 + items: + items: + - description: multiplier + minimum: 1 + - description: divisor + minimum: 1 + required: - compatible - - reg - "#clock-cells" - clocks - clock-names - xlnx,speed-grade - xlnx,nr-outputs +allOf: + - if: + required: + - xlnx,static-config + then: + required: + - xlnx,clk-mul-div + else: + required: + - reg + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + additionalProperties: false examples: - | - clock-controller@b0000000 { + clock-controller@b0000000 { compatible = "xlnx,clocking-wizard"; reg = <0xb0000000 0x10000>; #clock-cells = <1>; - xlnx,static-config; + clocks = <&clkc 15>, <&clkc 18>; + clock-names = "clk_in1", "s_axi_aclk"; + xlnx,nr-outputs = <6>; xlnx,speed-grade = <1>; + }; + + - | + clock-controller { + compatible = "xlnx,clocking-wizard"; + #clock-cells = <1>; + clocks = <&clkc 15>; + clock-names = "clk_in1"; xlnx,nr-outputs = <6>; - clock-names = "clk_in1", "s_axi_aclk"; - clocks = <&clkc 15>, <&clkc 15>; + xlnx,speed-grade = <1>; + xlnx,static-config; + xlnx,clk-mul-div = <12 1>, <10 2>, <8 1>, <6 1>, <4 2>, <2 1>; }; ... -- 2.34.1