From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 641DCC44506 for ; Thu, 9 Jul 2026 12:02:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=n3e/3Mz+2j77ICnsCAepz9q/sEHFkYkcB3C4JHFJ/B8=; b=jKZE60b36/NXN1Qy4nxEuk1IFF ZSJlcBzICWQPB3C1+Ay5QFePHsU+xJlzAZ2Fyj9NTo9ZhWBsId4wfFCGlErd1KJz8wyWOb+mEfcvy O9tKz1+NNES9eoEeaGreixoS9YZP58z7SL+Rj0IGxi8E2mJ37oTnb6iqs9a5jpdFH4+eZoE5GG6Po iqL8urta1zHvkj23b6N1UYAHVC5x7isli6JcUMn6ac8GX4D6b6/kKJx3piIDAt+m4UheFJq6RvUGe EmGz3tX9/QCD40ptkAFZRHKhxb/w1Gbz5dibNxjTX3D3wYjU1C3AtE/6vLj1lECyxRGMO1Ch/wF3B PGO61BDg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1whnRt-00000002IJR-22g2; Thu, 09 Jul 2026 12:01:49 +0000 Received: from mail-japaneastazlp170120005.outbound.protection.outlook.com ([2a01:111:f403:c405::5] helo=TYPPR03CU001.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1whnRp-00000002IHf-280r for linux-arm-kernel@lists.infradead.org; Thu, 09 Jul 2026 12:01:46 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=ILztavRi+AcxM60VK/xfnuCDgc2xC/ul77hUjOHhjhIPirOq8KwI4CW06IHgmSoZbeeqK4Aw8taVvW7qp0beZ5ORpzw3e7pdG+LtINEpV6A5bxQwVcpbSE/TXoFeCjbH6BAjck0uh+/f13kExXev00pTpuI3+xauTubq+xxYM1fg2DpOueHdjKPuPduEk6TtNCXgOtpXKEfUYWf6VslVwLwHqk1XbOH8sjA9Allo/I4joq1NNKcJhhyfh4zYVcCqZdKEKKDBBtL7jYb6mBQK5sxbGY4bd+fQJXxtEvC0yclahaLfgC65PNgIYXbbjeGCBkhDjOwj/aq378hLnqRf0w== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=n3e/3Mz+2j77ICnsCAepz9q/sEHFkYkcB3C4JHFJ/B8=; b=CmyNFT3T1DBQuOUtF3fX6FPXwWGISNLfghqg59D03iWYSfTOTWYNcxt26q3TUUP6tuDLlbbVtBN6M3XecvHKhKAZ+pE5BGNb3JY6/ltHwSzhfuvwS7qlfffPEpWFO7iIurG1dtv31hM8586jkNbW0IQJ3XCoYE9a8wxgnXChvlHRjTJOSFRCPPQVR7ViRXtHe4y1A3lx2NaeUTYdYywVByzCJ1OCiaGJuSUv0h9ogCAQxH0uRrvJtr15USRFESOGFaUiTId4TnOzJ+08Rrkpbhu7Cz15VIBNqDl7yayA8KhKXlgKnUKJ4vsN+WrjaQf1e17+t1jwkWTZsxGCcYlmqg== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=baylibre.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from PS2PR02CA0052.apcprd02.prod.outlook.com (2603:1096:300:5a::16) by SEZPR06MB8952.apcprd06.prod.outlook.com (2603:1096:101:33b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.181.15; Thu, 9 Jul 2026 12:01:31 +0000 Received: from OSA0EPF000000CB.apcprd02.prod.outlook.com (2603:1096:300:5a:cafe::44) by PS2PR02CA0052.outlook.office365.com (2603:1096:300:5a::16) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.202.10 via Frontend Transport; Thu, 9 Jul 2026 12:01:31 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by OSA0EPF000000CB.mail.protection.outlook.com (10.167.240.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.181.6 via Frontend Transport; Thu, 9 Jul 2026 12:01:30 +0000 Received: from cix (unknown [172.18.64.61]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 2EB244351F33; Thu, 9 Jul 2026 20:01:29 +0800 (CST) From: joakim.zhang@cixtech.com To: mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de Cc: cix-kernel-upstream@cixtech.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joakim Zhang , Krzysztof Kozlowski Subject: [PATCH v9 1/4] dt-bindings: soc: cix: add sky1 audss cru controller Date: Thu, 9 Jul 2026 20:01:22 +0800 Message-ID: <20260709120125.3997078-2-joakim.zhang@cixtech.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260709120125.3997078-1-joakim.zhang@cixtech.com> References: <20260709120125.3997078-1-joakim.zhang@cixtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: OSA0EPF000000CB:EE_|SEZPR06MB8952:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: 7686751e-4c54-433d-4fc0-08deddb1d092 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|82310400026|36860700016|376014|1800799024|23010399003|56012099006|3023799007|22082099003|18002099003|6133799003; X-Microsoft-Antispam-Message-Info: P17bNiLXHfE103LnWzKW/dw2qqFl5/Au9tIGJxb6wMD5F6FPed2Aj/BCE+vecm6DD6qc0VwUKxFZSuBHlqHF5X+az3iLcqoRdQt2f908urwfKKznhSYNQ2NKVg5N+A42hFDWXE9LtbGNSRDNjI/E2Poyqa1b3QP78OSlMhw9oyNhGyHDum2GGPqnLpAAWuAkikgV2VtYMhYquCnkjP5GnF8IHvXyXBxc3sbUUxHFMjZoKMBzxP7C1+I38Ydy8mKh7J31gBa9hKUdd0NyBdQAo8Cy0NuZknjwUNN956QhRbUPExQZaRExbJw1Uhud77OBzgtKMFP7943uNRRvg9T9KS1zh7M5Nj+P+pTRokIlyyr1/DiCUSZzW4jkWX3DvX2lD+j4hjDZTDL6FAdlI7vbXhruHbV8l2SXJOUzF3ziLM+3PE7unzb57h3kGX4CtAK8STVZNflS56hf2TXXuR6j2rr6f9Yzy0srKZL3ubdHxC2zRcS6zaE2H7RMmkMwR+++ViyyWmNoX9eKFEBFV3e8PnZ0N/GulMpd7aQqKRtDH3+yqXDUF68SKuFJzaN97ORt2z7EQRyfECz9cVKUOoiiZ/j2TlS22ix59SQxygtn1j4osmdIKRyLvImZnUzplp+AJ3BtzvmryTPCtKFdQKi1ZQ== X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(7416014)(82310400026)(36860700016)(376014)(1800799024)(23010399003)(56012099006)(3023799007)(22082099003)(18002099003)(6133799003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: tyP6vWJuQODEtPaBx8yF58RIs9hkg/jHE0utmvnsxrH86NF0HAgNPQb7C/gvi7kiMSaHMFCflPTwjfnarcd7tK1Pi0+SmMGBYiftDX/zTfJ8dr3/vePfg5sORlOUF/zx3a/JBPjuoDfT6QiEsES6Ahw/Dw2HIdCQJs+mISUhSy7TEPh4r8+xqoRmAB7jvb8BI7DPpchudBr/6hjkY6WC87kOoJ3jxVTS9pK4TT5V284Mdhhfy2HfHjcDRqbNOxEEW6hNIuEA1wc88wdDqP/alVUrTbKSBNUjsEwTydcgzA7KL61io6Ap4Mu8Q5rCLMcLpmopeQ9A6tvioKjkQU/bg1mD845JPsgyYuoTzNE3fAEE6RvPZPXcC0xijH25NhYpkj2Fpl86+vDm89ekAbTLr+Rk6HmqICjLiicr7v6LTKxJamt9n8AYNssUIL64zJ2P X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 09 Jul 2026 12:01:30.5214 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7686751e-4c54-433d-4fc0-08deddb1d092 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: OSA0EPF000000CB.apcprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR06MB8952 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260709_050145_552535_E5CC6FE1 X-CRM114-Status: GOOD ( 13.85 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Joakim Zhang The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU) groups clock muxing, gating and block-level software reset control in a single register block. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Joakim Zhang --- .../bindings/soc/cix/cix,sky1-audss-cru.yaml | 92 +++++++++++++++++++ .../dt-bindings/clock/cix,sky1-audss-cru.h | 60 ++++++++++++ .../dt-bindings/reset/cix,sky1-audss-cru.h | 25 +++++ 3 files changed, 177 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml create mode 100644 include/dt-bindings/clock/cix,sky1-audss-cru.h create mode 100644 include/dt-bindings/reset/cix,sky1-audss-cru.h diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml new file mode 100644 index 000000000000..50dd0593e1d9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/cix/cix,sky1-audss-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 audio subsystem clock and reset unit + +maintainers: + - Joakim Zhang + +description: | + The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU) groups + audio-related clock muxing, gating and block-level software reset control + in a single register block. + + A single device node exposes both the clock controller and software reset + lines. The clock driver registers as a platform driver; the reset controller + is registered by an auxiliary driver bound from the clock driver. + + Four SoC-level reference clocks listed in clocks/clock-names feed the AUDSS + clock tree. Internal AUDSS clocks are exposed via #clock-cells; indices are + defined in include/dt-bindings/clock/cix,sky1-audss-cru.h. + + Block-level software reset indices are exposed via #reset-cells; indices + are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h. + + The SoC syscon NoC (or bus) reset is described via resets. The audio + subsystem power domain is described via power-domains. + +properties: + compatible: + const: cix,sky1-audss-cru + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + Clock indices are defined in include/dt-bindings/clock/cix,sky1-audss-cru.h. + + '#reset-cells': + const: 1 + description: + Reset indices are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h. + + clocks: + items: + - description: I2S parent clock for sampling rates multiple of 8kHz. + - description: I2S parent clock for sampling rates multiple of 11.025kHz. + - description: Clock feeding most devices in AUDSS (NOC, DSP, SRAM, HDA, DMAC, I2S, and mailbox). + - description: Clock feeding HDA, timer and watchdog, which is a dedicated 48 MHz clock. + + clock-names: + items: + - const: x8k + - const: x11k + - const: sys + - const: 48m + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + audss_cru: clock-controller@7110000 { + compatible = "cix,sky1-audss-cru"; + reg = <0x7110000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk 76>, <&scmi_clk 78>, + <&scmi_clk 70>, <&scmi_clk 71>; + clock-names = "x8k", "x11k", "sys", "48m"; + power-domains = <&smc_devpd 0>; + resets = <&s5_syscon 31>; + }; diff --git a/include/dt-bindings/clock/cix,sky1-audss-cru.h b/include/dt-bindings/clock/cix,sky1-audss-cru.h new file mode 100644 index 000000000000..8c58ef8bf682 --- /dev/null +++ b/include/dt-bindings/clock/cix,sky1-audss-cru.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_CIX_SKY1_AUDSS_CRU_H +#define _DT_BINDINGS_CLOCK_CIX_SKY1_AUDSS_CRU_H + +#define CLK_AUD_CLK4_DIV2 0 +#define CLK_AUD_CLK4_DIV4 1 +#define CLK_AUD_CLK5_DIV2 2 + +#define CLK_DSP_CLK 3 +#define CLK_DSP_BCLK 4 +#define CLK_DSP_PBCLK 5 + +#define CLK_SRAM_AXI 6 + +#define CLK_HDA_SYS 7 +#define CLK_HDA_HDA 8 + +#define CLK_DMAC_AXI 9 + +#define CLK_WDG_APB 10 +#define CLK_WDG_WDG 11 + +#define CLK_TIMER_APB 12 +#define CLK_TIMER_TIMER 13 + +#define CLK_MB_0_APB 14 /* MB0: ap->dsp */ +#define CLK_MB_1_APB 15 /* MB1: dsp->ap */ + +#define CLK_I2S0_APB 16 +#define CLK_I2S1_APB 17 +#define CLK_I2S2_APB 18 +#define CLK_I2S3_APB 19 +#define CLK_I2S4_APB 20 +#define CLK_I2S5_APB 21 +#define CLK_I2S6_APB 22 +#define CLK_I2S7_APB 23 +#define CLK_I2S8_APB 24 +#define CLK_I2S9_APB 25 +#define CLK_I2S0 26 +#define CLK_I2S1 27 +#define CLK_I2S2 28 +#define CLK_I2S3 29 +#define CLK_I2S4 30 +#define CLK_I2S5 31 +#define CLK_I2S6 32 +#define CLK_I2S7 33 +#define CLK_I2S8 34 +#define CLK_I2S9 35 + +#define CLK_MCLK0 36 +#define CLK_MCLK1 37 +#define CLK_MCLK2 38 +#define CLK_MCLK3 39 +#define CLK_MCLK4 40 + +#endif diff --git a/include/dt-bindings/reset/cix,sky1-audss-cru.h b/include/dt-bindings/reset/cix,sky1-audss-cru.h new file mode 100644 index 000000000000..55e9f3797b30 --- /dev/null +++ b/include/dt-bindings/reset/cix,sky1-audss-cru.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ +#ifndef DT_BINDINGS_RESET_CIX_SKY1_AUDSS_CRU_H +#define DT_BINDINGS_RESET_CIX_SKY1_AUDSS_CRU_H + +#define AUDSS_I2S0_SW_RST 0 +#define AUDSS_I2S1_SW_RST 1 +#define AUDSS_I2S2_SW_RST 2 +#define AUDSS_I2S3_SW_RST 3 +#define AUDSS_I2S4_SW_RST 4 +#define AUDSS_I2S5_SW_RST 5 +#define AUDSS_I2S6_SW_RST 6 +#define AUDSS_I2S7_SW_RST 7 +#define AUDSS_I2S8_SW_RST 8 +#define AUDSS_I2S9_SW_RST 9 +#define AUDSS_WDT_SW_RST 10 +#define AUDSS_TIMER_SW_RST 11 +#define AUDSS_MB0_SW_RST 12 +#define AUDSS_MB1_SW_RST 13 +#define AUDSS_HDA_SW_RST 14 +#define AUDSS_DMAC_SW_RST 15 + +#endif -- 2.50.1