From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 06AF2C43458 for ; Tue, 14 Jul 2026 11:59:19 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:To:From:Reply-To: Cc:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=dta68QNbLoWzOS6PweKTXaAA6m2oOUeYKxDIVzU2tCk=; b=MK2iTaie/fTxofSsPro9KviBGH 6AsjJalHFp5VwFHAU6uGU+ddWyhAkIkgQMi0+UEHAVTnoDnT7y3G5yrq+IgmXg17ckyWfKcJ9Frnl svsOWOh+Q80DLhJJyYP5RsHsVo27HWztHahwU0M8TvrnUjBFBGRljTET3eqDzObd3qIDU+Hwib4vZ 3XPllisu09fiMYRww+w5A8oQ74uhTPKWU8u07QJ9ANZc+xNlp51DVWx3TemxA+05QKEbupEIzCr1V f1NzotGOMc6K1dw1fq93Zgt1o15FRRGW8zqDbTAfcJMfVjjPErw6X3A9pAUtq3nEx7kkcQkbCriCz mTPwU72w==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wjbn6-0000000Bp3j-3ps8; Tue, 14 Jul 2026 11:59:12 +0000 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wjbmx-0000000Bou6-3bQH for linux-arm-kernel@lists.infradead.org; Tue, 14 Jul 2026 11:59:06 +0000 Received: by mail-wm1-x331.google.com with SMTP id 5b1f17b1804b1-493c19bad03so38134535e9.2 for ; Tue, 14 Jul 2026 04:59:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20251104; t=1784030342; x=1784635142; darn=lists.infradead.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:from:to:cc:subject:date:message-id :reply-to:content-type; bh=dta68QNbLoWzOS6PweKTXaAA6m2oOUeYKxDIVzU2tCk=; b=PJcAvWPmNfFE+f3gZ2AC5Ml8YHdbG752/mAkWilQnYI0A53DVressfTKLImsKhVFFB JfVdH4RTM+J00Sw1iBwGn4WA8vw65+92JISTBiUU7LFn7F3s1mJdTVewtNmEhXzkHRCg AbBzBSVY1E00xngDI9r3AO5BMrR7qHR8tATzGY0vkSVkZlYKRyM1K3ood/54qbiXHeqd weysiWLDW43AFaeuPtpSt3aIeHQp2x+fEWpCh2yk0WY3VQlERFZprkE3MkpNzLmTAzwU aA5T3H64wLI6AYjB6tDKnIMGtvVFhHU3YH63n0K5lryyGVMEfZw3QKN0lM2D8O5DEqCq TU8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784030342; x=1784635142; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:to:from:x-gm-gg:x-gm-message-state:from:to :cc:subject:date:message-id:reply-to:content-type; bh=dta68QNbLoWzOS6PweKTXaAA6m2oOUeYKxDIVzU2tCk=; b=Ol6ZHkN8RpqWD+VUbrH9C5UyEiD3E89Bj0yFqprXDDkk+Dh6Mhduy4PyQLhuQyBxUx EjmkcbYUyUweynQ5+1Dsek4i/UMU5VGOSVMsmqxNCl4KkpjDdWDKy4VhBU1rFcCSxSFs tCbN04ayunh1kYtr9Us+Yx0anc7YZ3Wk0IhydyT7yha3Iu0vqPg7Ki206VIOKBxK7la1 MOPbmwdNqmfLTnMyUZ6kY3LAycXllYnvVTbJpqbqPZlVIq0tefFZXT7BD5/N9YVjeH8m aVBhcn9BaoEg3rJ5Y/O0MfOuVLxjX0oO6okBFol4ulG4AM9ApDU3NvV2sfzRJFyoAfJr P0FA== X-Forwarded-Encrypted: i=1; AHgh+RoBMAHuni+rxBR+9QBrqEKpbAX3BdJwyUTs2CqxF1meZ3zXGDYLLqg0DRU5KFFV8gO+C23kfYITLTgFMPpiFC1H@lists.infradead.org X-Gm-Message-State: AOJu0YxrjiZ/AG6OVeDemrYacMil9oZdCm2xTh/4gtUra0hwEoRhlRQ7 lfCq9s0Bu7tsiSNgD5foFUhO66vd46ciD7qEJt22P6WXda2W+fG8pjwn X-Gm-Gg: AfdE7cn89/f0HIkiwa3YLYlgpH9aB7dTiiQ0WOfext34pkBXsWTy6BvMzskpahpRw01 0FCQzwR9LCPO+Sm8ZA6yyX8XSf6y06Q2109/DlLzqlubE/Vf2v2X1ymOl32cSgksRD2hLqrAdGq oZ3VwpvGNfOePUK+5seOUjhB/eh1hrf2ua2EREWYlej4Sq4nQf3KH4j//R9XW78ySJrfpt4F367 Q7JtcqywQLh8iZ48HcKfbc89mrJBJIMkn8/ljhy4TcN/X0MCOcPVPA9yMXRM1+tnN06ZMHuaNhc RQiu2ZTCwXhVcSl8hN4TyXRW0dY/YBxQnYiTD/P+KB4iTtLs5XPoHBQ5HPonKpYzlscrKlizaXC v+mNXTDeEWhV3AiG9d+jJDfKiE3Cz7Q+rqqjLYamrqG1yd6T6iMoq0geTqWGYgXFsz7/rlaQg+a 3gRwxuCX9vF+y21sxa1r15vC4CZi+qd4Lgux6jrMmEVzbdmvPAhsl/mS5S8e2dNFK8uhXTgol24 QCaYPu/ X-Received: by 2002:a05:600c:a4a:b0:493:e9c2:ba60 with SMTP id 5b1f17b1804b1-493f8820ab3mr130769725e9.22.1784030341641; Tue, 14 Jul 2026 04:59:01 -0700 (PDT) Received: from Ansuel-XPS24.localdomain (host-95-248-227-210.retail.telecomitalia.it. [95.248.227.210]) by smtp.googlemail.com with ESMTPSA id 5b1f17b1804b1-493fd3ccfd4sm180531655e9.2.2026.07.14.04.59.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 14 Jul 2026 04:59:01 -0700 (PDT) From: Christian Marangi To: Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Michael Turquette , Stephen Boyd , Brian Masney , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v4 3/4] dt-bindings: PCI: mediatek-gen3: Split Airoha schema and document 2-lanes Date: Tue, 14 Jul 2026 13:58:45 +0200 Message-ID: <20260714115848.8537-4-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260714115848.8537-1-ansuelsmth@gmail.com> References: <20260714115848.8537-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260714_045904_964336_4AA2D2A5 X-CRM114-Status: GOOD ( 19.98 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To permit proper documentation of required property to support PCIe configured for 2-lanes mode, split the Airoha schema part from the mediatek-gen3 schema to a dedicated schema. A PCIe configured for 2-lanes mode require an additional reg for the secondary PCIe to be configured and the airoha,scu phandle to correctly configure the PCIe MUX. Rework the mediatek-gen3 schema to drop any redundant constraint previsouly introduced for Airoha PCIe properties. Signed-off-by: Christian Marangi --- .../bindings/pci/airoha,en7581-pcie.yaml | 244 ++++++++++++++++++ .../bindings/pci/mediatek-pcie-gen3.yaml | 77 +----- 2 files changed, 249 insertions(+), 72 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml b/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml new file mode 100644 index 000000000000..78a181a3b599 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml @@ -0,0 +1,244 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/airoha,en7581-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gen3 PCIe controller on Airoha SoCs + +maintainers: + - Christian Marangi + +description: |+ + PCIe Gen3 MAC controller for Airoha SoCs, it supports Gen3 speed + and compatible with Gen2, Gen1 speed. + + This PCIe controller supports up to 256 MSI vectors, the MSI hardware + block diagram is as follows: + + +-----+ + | GIC | + +-----+ + ^ + | + port->irq + | + +-+-+-+-+-+-+-+-+ + |0|1|2|3|4|5|6|7| (PCIe intc) + +-+-+-+-+-+-+-+-+ + ^ ^ ^ + | | ... | + +-------+ +------+ +-----------+ + | | | + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ + |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ + ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ + | | | | | | | | | | | | (MSI vectors) + | | | | | | | | | | | | + + (MSI SET0) (MSI SET1) ... (MSI SET7) + + With 256 MSI vectors supported, the MSI vectors are composed of 8 sets, + each set has its own address for MSI message, and supports 32 MSI vectors + to generate interrupt. + +properties: + compatible: + const: airoha,en7581-pcie + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + + ranges: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 4 + + reset-names: + minItems: 1 + maxItems: 4 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: sys-ck + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie-phy + + num-lanes: + enum: [1, 2] + + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + + airoha,scu: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to airoha SCU syscon + description: + Phandle to SCU syscon to configure PCIe MUX for 2 lines support. + + '#interrupt-cells': + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling INTx PCI interrupts. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - interrupt-controller + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - if: + properties: + num-lanes: + const: 2 + then: + properties: + reg: + minItems: 2 + + reg-names: + items: + - const: pcie-mac + - const: sec-pcie-mac + + resets: + minItems: 4 + + reset-names: + items: + - const: phy-lane0 + - const: phy-lane1 + - const: perstout + - const: sec-perstout + + required: + - airoha,scu + + else: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - const: pcie-mac + + resets: + minItems: 2 + maxItems: 3 + + reset-names: + minItems: 2 + items: + - enum: [ phy-lane0, phy-lane1, phy-lane2 ] + - enum: [ phy-lane1, perstout ] + - const: phy-lane2 + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1fc00000 { + compatible = "airoha,en7581-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + reg = <0x0 0x1fc00000 0x0 0x1670>, + <0x0 0x1fc20000 0x0 0x1670>; + reg-names = "pcie-mac", "sec-pcie-mac"; + + clocks = <&scuclk 7>; + clock-names = "sys-ck"; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + + ranges = <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000>; + + resets = <&scuclk 48>, + <&scuclk 49>, + <&scuclk 53>, + <&scuclk 54>; + reset-names = "phy-lane0", "phy-lane1", + "perstout", "sec-perstout"; + + num-lanes = <2>; + + mediatek,pbus-csr = <&pbus_csr 0x0 0x4>; + + airoha,scu = <&scuclk>; + + interrupts = ; + bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 4db700fc36ba..510f1f2b1c5a 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -59,7 +59,6 @@ properties: - const: mediatek,mt8196-pcie - const: mediatek,mt8192-pcie - const: mediatek,mt8196-pcie - - const: airoha,en7581-pcie reg: maxItems: 1 @@ -83,20 +82,20 @@ properties: resets: minItems: 1 - maxItems: 3 + maxItems: 2 reset-names: minItems: 1 - maxItems: 3 + maxItems: 2 items: - enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ] + enum: [ phy, mac ] clocks: - minItems: 1 + minItems: 4 maxItems: 6 clock-names: - minItems: 1 + minItems: 4 maxItems: 6 assigned-clocks: @@ -115,17 +114,6 @@ properties: power-domains: maxItems: 1 - mediatek,pbus-csr: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - - items: - - description: phandle to pbus-csr syscon - - description: offset of pbus-csr base address register - - description: offset of pbus-csr base address mask register - description: - Phandle with two arguments to the syscon node used to detect if - a given address is accessible on PCIe controller. - '#interrupt-cells': const: 1 @@ -177,16 +165,6 @@ allOf: - const: peri_26m - const: top_133m - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - if: properties: compatible: @@ -208,16 +186,6 @@ allOf: - const: peri_26m - const: peri_mem - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - if: properties: compatible: @@ -246,8 +214,6 @@ allOf: - const: phy - const: mac - mediatek,pbus-csr: false - - if: properties: compatible: @@ -257,7 +223,6 @@ allOf: then: properties: clocks: - minItems: 4 maxItems: 4 clock-names: @@ -267,38 +232,6 @@ allOf: - const: peri_26m - const: top_133m - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - - if: - properties: - compatible: - const: airoha,en7581-pcie - then: - properties: - clocks: - maxItems: 1 - - clock-names: - items: - - const: sys-ck - - resets: - minItems: 3 - - reset-names: - items: - - const: phy-lane0 - - const: phy-lane1 - - const: phy-lane2 - unevaluatedProperties: false examples: -- 2.53.0