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Signed-off-by: Neha Malcom Francis Signed-off-by: Gandhar Deshpande Signed-off-by: MANNURU VENKATESWARLU --- .../memory-controllers/ti/ti,j7-ddrss.yaml | 186 ++++++++++++++++++ 1 file changed, 186 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml diff --git a/Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml b/Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml new file mode 100644 index 0000000000000..f4bebabaeb111 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti/ti,j7-ddrss.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/ti/ti,j7-ddrss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI wrapper module for the Cadence DDRSS controller + +maintainers: + - Santhosh Kumar K + - Neha Malcom Francis + +description: | + The K3 DDR subsystem comprises DDR controller, DDR PHY and wrapper + logic to integrate these blocks in the device. The DDR subsystem is + used to provide an interface to external SDRAM devices which can be + utilized for storing program or data. + +properties: + compatible: + oneOf: + - enum: + - ti,j721s2-ddrss + - ti,j721e-ddrss + - ti,j7-ddrss + - ti,am62-ddrss + - ti,am62a-ddrss + - items: + - const: ti,am64-ddrss + - const: ti,am62-ddrss + - items: + - const: ti,am62p-ddrss + - const: ti,am62a-ddrss + + reg: + minItems: 1 + maxItems: 3 + description: | + Register regions for the DDR subsystem wrapper. The number of regions + depends on the SoC variant: + - 1 region (ss_cfg): am62, am62p legacy layout + - 2 regions (cfg, ctrl_mmr_lp4): j7200, j721e + - 3 regions (cfg, ctrl_mmr_lp4, ss_cfg): j721s2, j784s4, am62a, am64 + + reg-names: + oneOf: + - items: + - const: ss_cfg + - items: + - const: cfg + - const: ctrl_mmr_lp4 + - items: + - const: cfg + - const: ctrl_mmr_lp4 + - const: ss_cfg + + bootph-pre-ram: true + + ranges: + minItems: 1 + + interrupts: + maxItems: 1 + description: | + Interrupt line for the DDR subsystem controller. This interrupt is + typically used for temperature monitoring and error reporting. + + power-domains: + minItems: 1 + maxItems: 2 + description: | + Power domains required by the DDR subsystem: + - an entry to TISCI DDR CFG device + - an entry to TISCI DDR DATA. + + clocks: + minItems: 1 + maxItems: 2 + description: | + - An entry to DDRSS clock + - An entry to SoC bypass clock + + ti,ddr-freq0: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Initial DDR frequency in Hz before frequency switching. Present on + SoCs with three-frequency operation (j721s2, j784s4). + + ti,ddr-freq1: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Primary DDR frequency setting in Hz. This value is used for + normal operation of the DDR subsystem. + + ti,ddr-freq2: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Secondary DDR frequency setting in Hz. This value can be used + for power saving or performance modes. + + ti,ddr-fhs-cnt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: | + Frequency handover sequence count. This value defines how many + steps to use when switching between frequency settings. + + instance: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Zero-based index identifying this DDR subsystem instance. Required on + multi-DDR SoCs (j721s2, j784s4) where two or more instances exist. + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + +patternProperties: + "^ddr@": + type: object + + "^ddr-pmu@": + type: object + properties: + compatible: + const: ti,k3-ddr-pmu + reg: + maxItems: 1 + required: + - compatible + - reg + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - ranges + - interrupts + - power-domains + - clocks + +additionalProperties: false + +examples: + - | + #include + #include + + cbass_main { + #address-cells = <2>; + #size-cells = <2>; + + memorycontroller: memorycontroller@2980000 { + compatible = "ti,j721e-ddrss"; + reg = <0x0 0x02990000 0x0 0x4000>, + <0x0 0x0114000 0x0 0x100>; + reg-names = "cfg", "ctrl_mmr_lp4"; + power-domains = <&k3_pds 47 TI_SCI_PD_SHARED>, + <&k3_pds 90 TI_SCI_PD_SHARED>; + interrupts = ; + #address-cells = <2>; + #size-cells = <2>; + ranges = <0x00 0x0000 0x00 0x02990000 0x00 0x4000>; + ti,ddr-freq1 = <0>; + ti,ddr-freq2 = <0>; + ti,ddr-fhs-cnt = <0>; + clocks = <&k3_clks 47 2>, <&k3_clks 30 9>; + bootph-pre-ram; + + ddr: ddr@0 { + compatible = "cdns,k3-ddr"; + reg = <0x00 0x0000 0x00 0x72c>, + <0x00 0x2000 0x00 0x4b0>, + <0x00 0x4000 0x00 0x163c>; + reg-names = "ctl_cfg", "ctl_cfg_pi", "ctl_cfg_phy"; + bootph-pre-ram; + }; + + ddr_pmu0: ddr-pmu@100 { + compatible = "ti,k3-ddr-pmu"; + reg = <0x00 0x100 0x00 0x14>; + }; + }; + }; -- 2.34.1