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The previous node only mapped the last 4 KB (0x2201f000, 0x1000) which was used for the SCMI shared memory buffer. Update the base address and size to cover the full P2 region so it can also serve as a general purpose SRAM pool. Signed-off-by: Peng Fan --- arch/arm64/boot/dts/freescale/imx8ulp.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi index c82c3388cbe79..173d11dea5d4f 100644 --- a/arch/arm64/boot/dts/freescale/imx8ulp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8ulp.dtsi @@ -154,9 +154,9 @@ sosc: clock-sosc { #clock-cells = <0>; }; - sram@2201f000 { + sram@22010000 { compatible = "mmio-sram"; - reg = <0x0 0x2201f000 0x0 0x1000>; + reg = <0x0 0x22010000 0x0 0x10000>; #address-cells = <1>; #size-cells = <1>; -- 2.34.1