From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id A60B6C44508 for ; Wed, 15 Jul 2026 12:00:24 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type:Cc:To:From: Subject:Message-ID:References:Mime-Version:In-Reply-To:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=3arABq/LbCnYkg13T0a9RWMUKBWAd4ICzVlPWgUKHjA=; b=1wnvxGlfa6UEIY9rBgcN2fLs2G 920VixAF3oFNXE0gZ/iD8SMf4kaEEwCs0agZZLHkEtK0j0WpENgUihNF9HHe8JBd1pF1gY5bYgzA/ X2gIa5bQIa/iiJFtoJxCrMLjbA7RjGY5QLf12NayEK1guBcU50Ih5uRlUljIWKmajiTL3Yn/5iwIc C1gInZ/TC/5VEfXkPevTLoDpCpJRiP+yDIbvZtzPZmkShHG/QrFpSFbIxGUicUFFIT+knwtSf4ifo 1deyWyuh0CF6ohisQnThW7MUvVjZoSlRU2dJq7tuUpJQrPLlkOKZPXIG1PYU8IAw1qLZi7e2hlv7N uASV+93Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wjyHX-0000000EfqU-46Ji; Wed, 15 Jul 2026 12:00:08 +0000 Received: from mail-wm1-x349.google.com ([2a00:1450:4864:20::349]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wjyH4-0000000EfJr-37hT for linux-arm-kernel@lists.infradead.org; Wed, 15 Jul 2026 11:59:42 +0000 Received: by mail-wm1-x349.google.com with SMTP id 5b1f17b1804b1-493bc2b376fso40903675e9.3 for ; Wed, 15 Jul 2026 04:59:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20251104; t=1784116777; x=1784721577; darn=lists.infradead.org; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:from:to:cc:subject:date:message-id:reply-to :content-type; bh=3arABq/LbCnYkg13T0a9RWMUKBWAd4ICzVlPWgUKHjA=; b=XXxlOk+D719mQRHqDi0NDRnry2YIzYlmsE2crArEqjJt7iWV7ugzPGohOONJSa7gD4 MOu4cmv+PpRRjCr4sWf23o/ixw1Wo1R0C1U09VWQsGvzQooWVxgyzn0Oak05HhnJiIHW eiP4fV8dKhC0WPW4eXhHEnUKrNAh2vg1Y9X3hAHVRhw46LpuVTqYIj2nCoog85RcU3WM FnZwP/fcAbi8ukCqYWlm+w6LE2w9JjIPPVfLU1Ep8yxbLllvZbqNwe9JCOivcRWdokrh PH07gZ0elRRRV0mT/lhk+1h2PUFFzwFh9IY1urMAREQ+IlG59XQb+VgAbhCUpB59hmnL OcNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20251104; t=1784116777; x=1784721577; h=content-type:cc:to:from:subject:message-id:references:mime-version :in-reply-to:date:x-gm-message-state:from:to:cc:subject:date :message-id:reply-to:content-type; bh=3arABq/LbCnYkg13T0a9RWMUKBWAd4ICzVlPWgUKHjA=; b=hsPeEdpZB+0tFHt33AwdRf/9EQ0rtXzojBLzAdagMGEJmS1H5zhnuTNHUo2cQmilP2 VBSwzCzc/9CzY9H0xRfYVcPfzhR6w0b/gGHDyhkFfKK7vQha4R6Fr5rgpjEXkQXHyVZC ir8i4ziarT+qrXBhjuGOarMIFtDyLJaXcub6rSP5hcTBTRxA+bGfyi31bfrgrm5gyk5s rfWJdMu0HcklkYQd3Mz6F35XDBml/c14/SVdELgPPCa9M0SxYCA4VdLogOrCV13Vlf2T goHl6BYiYXd4GJjBjoB+kO/F4lFjcwLG/T9noA6n9xc98WAlbZ/UOL8ZcDBuMTM24RxX 3euw== X-Gm-Message-State: AOJu0YzW18M6F5HJAN5Rf9weDE+TQo0UhXc3duwqn8WEYYPMkVt9mpED b5NkHcrA/OiqMlgQKU/fpR9ZH7ZGLryOmeyfcgr3Vjn0hejXiLlaT3MhsKxvhZkiDrRSOzDVg0n ucF/0H78GqohoBGRY41q4rpxgcySmCtvRTjWrVppyXZZrvEH1F3OicYf/XPXtMnxJB48Osi8Zzz dZdbHP8B1B7W37UGvfjuzEu5xJ34V/7leQp12u8P7CJAsqcchPT+6BJSq2zookAH5yJA== X-Received: from wmbdx5.prod.google.com ([2002:a05:600c:63c5:b0:493:f781:b52f]) (user=smostafa job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600d:6446:20b0:493:e034:a3b5 with SMTP id 5b1f17b1804b1-4953c27ab18mr21837125e9.24.1784116776358; Wed, 15 Jul 2026 04:59:36 -0700 (PDT) Date: Wed, 15 Jul 2026 11:58:59 +0000 In-Reply-To: <20260715115906.2664882-1-smostafa@google.com> Mime-Version: 1.0 References: <20260715115906.2664882-1-smostafa@google.com> X-Mailer: git-send-email 2.55.0.141.g00534a21ce-goog Message-ID: <20260715115906.2664882-19-smostafa@google.com> Subject: [PATCH v7 18/24] iommu/arm-smmu-v3-kvm: Shadow STEs From: Mostafa Saleh To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, iommu@lists.linux.dev Cc: catalin.marinas@arm.com, will@kernel.org, maz@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, joro@8bytes.org, jgg@ziepe.ca, mark.rutland@arm.com, qperret@google.com, tabba@google.com, vdonnefort@google.com, sebastianene@google.com, keirf@google.com, Mostafa Saleh Content-Type: text/plain; charset="UTF-8" X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260715_045938_846546_C2A53947 X-CRM114-Status: GOOD ( 21.37 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add STE emulation, when the host sends the CFGI_STE command. Copy the STE as is to the shadow owned by the hypervisor, in the next patch, stage-2 page table will be attached. Signed-off-by: Mostafa Saleh --- .../iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c | 127 +++++++++++++++++- 1 file changed, 121 insertions(+), 6 deletions(-) diff --git a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c index 3b133f24b4ca..fba3b3e15780 100644 --- a/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c +++ b/drivers/iommu/arm/arm-smmu-v3/pkvm/arm-smmu-v3.c @@ -23,6 +23,9 @@ struct hyp_arm_smmu_v3_device *kvm_hyp_arm_smmu_v3_smmus; #define strtab_split(smmu) (FIELD_GET(STRTAB_BASE_CFG_SPLIT, (smmu)->host_ste_cfg)) #define strtab_l1_size(smmu) ((1UL << (strtab_log2size(smmu) - strtab_split(smmu))) * \ (sizeof(struct arm_smmu_strtab_l1))) +#define strtab_hyp_base(smmu) ((smmu)->features & ARM_SMMU_FEAT_2_LVL_STRTAB ? \ + (u64 *)(smmu)->strtab_cfg.l2.l1tab :\ + (u64 *)(smmu)->strtab_cfg.linear.table) #define for_each_smmu(smmu) \ for ((smmu) = kvm_hyp_arm_smmu_v3_smmus; \ @@ -283,6 +286,94 @@ static int smmu_init_cmdq(struct hyp_arm_smmu_v3_device *smmu) return 0; } +static int smmu_get_host_l2_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, + struct arm_smmu_ste *host_ste_out) +{ + u64 *host_ste_base = hyp_phys_to_virt(strtab_host_base(smmu)); + struct arm_smmu_strtab_l1 host_l1_desc; + struct arm_smmu_strtab_l2 *l2ptr; + phys_addr_t host_l2_tab; + int ret, i; + + host_l1_desc.l2ptr = READ_ONCE(host_ste_base[arm_smmu_strtab_l1_idx(sid)]); + if (!(le64_to_cpu(host_l1_desc.l2ptr) & STRTAB_L1_DESC_SPAN)) + return -EINVAL; + + host_l2_tab = le64_to_cpu(host_l1_desc.l2ptr) & STRTAB_L1_DESC_L2PTR_MASK; + /* Share and pin the table before accessing it. */ + ret = smmu_share_pages(host_l2_tab, sizeof(struct arm_smmu_strtab_l2)); + if (ret) + return ret; + + l2ptr = hyp_phys_to_virt(host_l2_tab); + + for (i = 0 ; i < STRTAB_STE_DWORDS ; ++i) + host_ste_out->data[i] = + READ_ONCE(l2ptr->stes[arm_smmu_strtab_l2_idx(sid)].data[i]); + + WARN_ON(smmu_unshare_pages(host_l2_tab, sizeof(struct arm_smmu_strtab_l2))); + return 0; +} + +static int smmu_reshadow_ste(struct hyp_arm_smmu_v3_device *smmu, u32 sid, bool leaf) +{ + struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; + struct arm_smmu_ste *hyp_ste_ptr, *host_ste_ptr, host_ste_copy; + u64 *hyp_ste_base = strtab_hyp_base(smmu); + int ret, i; + + /* + * Linux only uses leaf = 1, when leaf is 0, we need to verify that this + * is a 2 level table and reshadow of l2. + * Also, we rely on Linux only issuing CFGI_STE to attach a device when + * the SMMU is enabled. + */ + if (!leaf || !is_smmu_enabled(smmu) || + (sid >= (1UL << strtab_log2size(smmu)))) + return -EINVAL; + + if (!(smmu->features & ARM_SMMU_FEAT_2_LVL_STRTAB)) { + struct arm_smmu_ste *hyp_table = (struct arm_smmu_ste *)hyp_ste_base; + u64 *host_ste_base = hyp_phys_to_virt(strtab_host_base(smmu)); + struct arm_smmu_ste *host_table = (struct arm_smmu_ste *)host_ste_base; + + if (sid >= cfg->linear.num_ents) + return -E2BIG; + + hyp_ste_ptr = &hyp_table[sid]; + host_ste_ptr = &host_table[sid]; + } else { + struct arm_smmu_strtab_l1 *l1tab = (struct arm_smmu_strtab_l1 *)hyp_ste_base; + u32 l1_idx = arm_smmu_strtab_l1_idx(sid); + struct arm_smmu_strtab_l2 *l2ptr; + + if (l1_idx >= cfg->l2.num_l1_ents) + return -E2BIG; + + host_ste_ptr = &host_ste_copy; + ret = smmu_get_host_l2_ste(smmu, sid, host_ste_ptr); + if (ret) + return ret; + + if (!l1tab[l1_idx].l2ptr) { + struct arm_smmu_strtab_l2 *l2table; + + /* No hypervisor entry, first time the L2 is populated. */ + l2table = pkvm_iommu_donate_pages(get_order(sizeof(*l2table))); + if (!l2table) + return -ENOMEM; + arm_smmu_write_strtab_l1_desc(&l1tab[l1_idx], hyp_virt_to_phys(l2table)); + } + l2ptr = hyp_phys_to_virt(le64_to_cpu(l1tab[l1_idx].l2ptr) & + STRTAB_L1_DESC_L2PTR_MASK); + hyp_ste_ptr = &l2ptr->stes[arm_smmu_strtab_l2_idx(sid)]; + } + + for (i = 0 ; i < STRTAB_STE_DWORDS ; ++i) + WRITE_ONCE(hyp_ste_ptr->data[i], host_ste_ptr->data[i]); + return 0; +} + static int smmu_init_strtab(struct hyp_arm_smmu_v3_device *smmu) { struct arm_smmu_strtab_cfg *cfg = &smmu->strtab_cfg; @@ -396,8 +487,24 @@ static bool smmu_filter_command(struct hyp_arm_smmu_v3_device *smmu, u64 *comman switch (type) { case CMDQ_OP_CFGI_STE: - /* TBD: SHADOW_STE*/ + { + u32 leaf = FIELD_GET(CMDQ_CFGI_1_LEAF, command[1]); + u32 sid = FIELD_GET(CMDQ_CFGI_0_SID, command[0]); + bool ret; + + /* + * If STE update is required flush the CMDQ and drop the lock as that + * might require to update the host page table and aquire its lock. + */ + writel(smmu->cmdq.llq.prod, smmu->cmdq.prod_reg); + hyp_spin_unlock(&smmu->hw_lock); + ret = smmu_reshadow_ste(smmu, sid, leaf); + hyp_spin_lock(&smmu->hw_lock); + if (ret) + return true; + break; + } case CMDQ_OP_CFGI_ALL: { /* @@ -608,25 +715,33 @@ static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, val = smmu->cmdq_host.llq.cons | (CMDQ_CONS_ERR & cons); goto out_update_regs; } - /* Passthrough the register access for bisectiblity, handled later */ case ARM_SMMU_STRTAB_BASE: + if (len != sizeof(u64)) + break; if (is_write) { /* Must only be written when SMMU_CR0.SMMUEN == 0.*/ if (is_smmu_enabled(smmu)) break; smmu->host_ste_base = val; + goto out_ret; + } else { + val = smmu->host_ste_base; + goto out_update_regs; } - mask = read_write; - break; case ARM_SMMU_STRTAB_BASE_CFG: + if (len != sizeof(u32)) + break; if (is_write) { /* Must only be written when SMMU_CR0.SMMUEN == 0.*/ if (is_smmu_enabled(smmu)) break; smmu->host_ste_cfg = val; + goto out_ret; + } else { + val = smmu->host_ste_cfg; + goto out_update_regs; } - mask = read_write; - break; + /* Passthrough the register access for bisectiblity, handled later */ case ARM_SMMU_GBPA: mask = read_write; break; -- 2.55.0.141.g00534a21ce-goog