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Thu, 16 Jul 2026 14:35:50 -0700 (PDT) Received: from [192.168.0.2] ([197.250.51.119]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47f464b7f09sm27517548f8f.26.2026.07.16.14.35.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Jul 2026 14:35:49 -0700 (PDT) From: =?utf-8?q?Stefan_D=C3=B6singer?= Subject: [PATCH v7 00/13] ZTE zx297520v3 clock bindings and driver Date: Fri, 17 Jul 2026 00:35:36 +0300 Message-Id: <20260717-zx29clk-v7-0-408411cfcf36@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit X-B4-Tracking: v=1; b=H4sIAAAAAAAC/2XOy07DMBAF0F+pvCbIHr8yXfEfiIUfM60FbSEpU aHqv+OmC0dheUc+1/cqRhoKjWK7uYqBpjKW07EG/7QRaR+OO+pKrlmABCetkt3vBTB9vHdAJms kraBPor7+HIjLZW56fXvkgb6+a+H5cRQxjNSl0+FQzttNJPJOZ8vaqIiY2HgITNHKPhvse3YQX ApK3Lv2ZTyfhp955KTmsn97JtXJjlQMiZkJnX/ZHUL5eK4fzh0TLJ1qDqoDZEk5aSnZrp1eOMD mdHXJM1lDQdfBa2eac8o1Z+4uIJqYAQjz2tmFg745W51HZmkMGYWwdq45L6E5V532PnppuJfJL N3tdvsD/qAbBgICAAA= X-Change-ID: 20260510-zx29clk-2e4d39e3128c To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Brian Masney , Vinod Koul , Neil Armstrong , Russell King Cc: linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-phy@lists.infradead.org, =?utf-8?q?Stefan_D=C3=B6singer?= X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; 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a=openpgp; fpr=4F9C2C8728019633893EBBB98CB81F9A72BBA155 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260716_143552_620868_65B78EF1 X-CRM114-Status: GOOD ( 19.44 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi, I am sending version 7 of my zx297520v3 clock patch. The main change vs v6 is the reverse engineering of the PLL input and forward gates in top+0x140 and according reduction of the input clocks in the matrix binding. I think the list of clocks in my driver is fairly complete; It is certainly a lot better than what the downstream ZTE drivers have. I deduced a lot of it by trial and error. I am sure there are some clocks missing that will need to be added to the binding later. Afaiu adding clocks is not an issue, but removing or reordering them is an ABI break. Signed-off-by: Stefan Dösinger --- Changes in v7: *) Moved DT bindings back to clock/ (Krzysztof) *) Added a usb-phy child node to top to expose the USB status register *) Add clock gates that control input of PLL clocks into topcrm and forward to matrixcrm. Strip down matrixcrm inputs in the bindings to the known clocks in this register *) Add DDR clocks and resets, arm arch timer clock. They are marked critical and tell CCF not to gate off the aforementioned input/forward gates *) Remove syscon from matrixcrm (Krzysztof). The DDR mailbox system is on a different controller (soc_sys at 0x140000). ZTE's code merely controlled clocks in matrixcrm, which doesn't require syscon on this controller. *) Consistenly use double quotes in bindings and full include paths (Krzysztof) The individual patches call out changes in more detail. - Link to v6: https://lore.kernel.org/r/20260702-zx29clk-v6-0-377b704f80c4@gmail.com Changes in v6: *) Use MFD for all 3 controllers - I hope both Conor and Philipp will agree. I kept top and matrix bindings in soc/zte and lsp in clock/ though. *) Clean up issues found by Sashiko. I pointed them out in the individual patches. They are localized fixes and don't affect the overall design *)small code consistency: Changed "zx297520v3_lsp" to use "-" , "rst" in driver names to "reset" Changes in v5: *) Use MFD instead of aux bus for top and matrix clocks *) Move top and matrix bindings to soc/zte *) Give USB PHY its own resets *) Other localized changes are noted in the individual patches - Link to v4: https://lore.kernel.org/r/20260616-zx29clk-v4-0-ca994bd22e9d@gmail.com Changes in v4: *) Use syscon and regmap instead of raw IO *) Move reset to its own driver on the aux bus, but keep reset and clk in the same binding as it matches the way the hardware works *) Go back to having matrixclk in its own device because syscon deals poorly with multi io reg devices. List all PLL outputs from topclk as inputs to matrixclk *) Some more hardware research: Figure out the parents of the 4 possible GPIO clock outputs and declare them in the driver. They are unused on the hardware I have, but they show that all PLLs can be used. - Link to v3: https://lore.kernel.org/r/20260529-zx29clk-v3-0-c7fe54ea388f@gmail.com Changes in v3: Model top and matrix clocks as one device Add PLL driver Fixed a few issues found by Sashiko: register lock, some missing devm_, error handling v2: Fix build issues introduced by checkpatch.pl fixes that I didn't spot earlier. --- Stefan Dösinger (13): dt-bindings: phy: Add zx297520v3 USB phy documentation dt-bindings: clk: zte: Add zx297520v3 top clock and reset controller dt-bindings: clk: zte: Add zx297520v3 matrix clock and reset controller dt-bindings: clk: zte: Add zx297520v3 LSP clock and reset controller mfd: zx297520v3: Add a clock and reset MFD driver clk: zte: Add Clock registration infrastructure clk: zte: Add regmap based clocks clk: zte: Add zx PLL support infrastructure clk: zte: Introduce a driver for zx297520v3 top clocks clk: zte: Introduce a driver for zx297520v3 matrix clocks clk: zte: Introduce a driver for zx297520v3 LSP clocks reset: zte: Add a zx297520v3 reset driver ARM: dts: zte: Declare zx297520v3 CRM device nodes .../bindings/clock/zte,zx297520v3-lspcrm.yaml | 101 ++ .../bindings/clock/zte,zx297520v3-matrixcrm.yaml | 91 ++ .../bindings/clock/zte,zx297520v3-topcrm.yaml | 123 +++ .../bindings/phy/zte,zx297520v3-usb-phy.yaml | 96 ++ MAINTAINERS | 10 + arch/arm/boot/dts/zte/zx297520v3.dtsi | 92 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/zte/Kconfig | 27 + drivers/clk/zte/Makefile | 6 + drivers/clk/zte/clk-regmap.c | 246 +++++ drivers/clk/zte/clk-zx.c | 155 +++ drivers/clk/zte/clk-zx.h | 90 ++ drivers/clk/zte/clk-zx297520v3.c | 1045 ++++++++++++++++++++ drivers/clk/zte/pll-zx.c | 520 ++++++++++ drivers/reset/Kconfig | 10 + drivers/reset/Makefile | 1 + drivers/reset/reset-zte-zx297520v3.c | 237 +++++ drivers/soc/Kconfig | 1 + drivers/soc/Makefile | 1 + drivers/soc/zte/Kconfig | 20 + drivers/soc/zte/Makefile | 3 + drivers/soc/zte/zx297520v3-crm.c | 99 ++ include/dt-bindings/clock/zte,zx297520v3-clk.h | 144 +++ include/dt-bindings/phy/phy-zte-zx297520v3-usb.h | 12 + include/dt-bindings/reset/zte,zx297520v3-reset.h | 63 ++ 26 files changed, 3187 insertions(+), 8 deletions(-) --- base-commit: bee763d5f341b99cf472afeb508d4988f62a6ca1 change-id: 20260510-zx29clk-2e4d39e3128c Best regards, -- Stefan Dösinger