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From: Francesco Dolcini <francesco@dolcini.it>
To: Leonardo Costa <leoreis.costa@gmail.com>, bhelgaas@google.com
Cc: hongxing.zhu@oss.nxp.com, frank.li@nxp.com,
	l.stach@pengutronix.de, lpieralisi@kernel.org,
	kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org,
	s.hauer@pengutronix.de, kernel@pengutronix.de,
	festevam@gmail.com, linux-pci@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev,
	linux-kernel@vger.kernel.org, Richard Zhu <hongxing.zhu@nxp.com>,
	leonardo.costa@toradex.com
Subject: Re: [PATCH v2] PCI: imx6: Fix i.MX6Q/DL boot hang by separating PHY power and reference clock control
Date: Fri, 17 Jul 2026 08:10:24 +0200	[thread overview]
Message-ID: <20260717061024.GA362793@francesco-nb> (raw)
In-Reply-To: <blkjlbskmfiyprh6wlbfilwlgjw3zkbslh6fpogcc5vcfu5dvn@hcrojgleuxob>



On Thu, Jul 16, 2026 at 11:43:31AM -0300, Leonardo Costa wrote:
> On Wed, Jul 08, 2026 at 11:59:27AM +0800, hongxing.zhu@oss.nxp.com wrote:
> > From: Richard Zhu <hongxing.zhu@nxp.com>
> > 
> > Commit 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling regulators")
> > introduced a boot hang on i.MX6Q/DL variants by changing the initialization
> > sequence.
> > 
> > The issue stems from coupling PHY power (TEST_PD) and reference clock
> > (REF_CLK_EN) control in imx6q_pcie_enable_ref_clk(). When these are
> > managed together, the timing between PHY power-up and reference clock
> > enablement cannot be properly controlled, leading to initialization
> > failures.
> > 
> > Fix this by separating the two concerns:
> > 
> > - Move PHY power control (TEST_PD) to imx6q_pcie_core_reset() where it
> >   logically belongs with reset operations. This ensures PHY power state
> >   is managed as part of the core reset sequence.
> > 
> > - Update imx6qp_pcie_core_reset() to call imx6q_pcie_core_reset() for
> >   shared PHY power management, avoiding code duplication.
> > 
> > - Make imx6q_pcie_enable_ref_clk() responsible only for reference clock
> >   (REF_CLK_EN) control, simplifying its purpose.
> > 
> > - Remove the 10us delay workaround from imx6q_pcie_enable_ref_clk() as
> >   proper sequencing is now handled by the core_reset functions.
> > 
> > This refactoring ensures PHY power is controlled during reset
> > operations, fixing the boot hang while improving code maintainability.
> > 
> > Fixes: 610fa91d9863 ("PCI: imx6: Assert PERST# before enabling regulators")
> > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
> > ---
> 
> Tested-by: Leonardo Costa <leonardo.costa@toradex.com>

Reported-by: Leonardo Costa <leoreis.costa@gmail.com>
Closes: https://lore.kernel.org/lkml/20260629143439.361560-1-leoreis.costa@gmail.com/

Bjorn: this should solve the concerns your questions from https://lore.kernel.org/lkml/20260716172858.GA111215@bhelgaas/

Francesco



  reply	other threads:[~2026-07-17  6:14 UTC|newest]

Thread overview: 15+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-07-08  3:59 [PATCH v2] PCI: imx6: Add runtime PM support for i.MX95 hongxing.zhu
2026-07-08  3:59 ` [PATCH v2] PCI: imx6: Fix i.MX6Q/DL boot hang by separating PHY power and reference clock control hongxing.zhu
2026-07-08 15:28   ` Frank Li
2026-07-14 12:51   ` Francesco Dolcini
2026-07-15  1:38     ` Hongxing Zhu (OSS)
2026-07-16 14:43   ` Leonardo Costa
2026-07-17  6:10     ` Francesco Dolcini [this message]
2026-07-16 16:35   ` Manivannan Sadhasivam
2026-07-17  8:57     ` Hongxing Zhu (OSS)
2026-07-08  3:59 ` [PATCH v2] PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability hongxing.zhu
2026-07-08 15:19   ` Frank Li
2026-07-09  7:55     ` Hongxing Zhu (OSS)
2026-07-09 15:08       ` Frank Li
2026-07-16 16:43 ` [PATCH v2] PCI: imx6: Add runtime PM support for i.MX95 Manivannan Sadhasivam
2026-07-17  2:34   ` Hongxing Zhu (OSS)

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