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client-ip=165.204.84.17; helo=satlexmb08.amd.com; pr=C Received: from satlexmb08.amd.com (165.204.84.17) by CY4PEPF0000EDD4.mail.protection.outlook.com (10.167.241.200) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Fri, 17 Jul 2026 09:08:45 +0000 Received: from satlexmb07.amd.com (10.181.42.216) by satlexmb08.amd.com (10.181.42.217) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.41; Fri, 17 Jul 2026 04:08:34 -0500 Received: from xhdsneeli40.xilinx.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server id 15.2.2562.41 via Frontend Transport; Fri, 17 Jul 2026 04:08:30 -0500 From: Srinivas Neeli To: Vinod Koul , Radhey Shyam Pandey CC: Frank Li , Michal Simek , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Suraj Gupta , Marek Vasut , Tomi Valkeinen , Alex Bereza , "Folker Schwesinger" , , , , , Subject: [PATCH v5 1/4] dmaengine: xilinx_dma: Fix MCDMA descriptor fields based on DMA direction Date: Fri, 17 Jul 2026 14:38:21 +0530 Message-ID: <20260717090824.2364230-2-srinivas.neeli@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260717090824.2364230-1-srinivas.neeli@amd.com> References: <20260717090824.2364230-1-srinivas.neeli@amd.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY4PEPF0000EDD4:EE_|CY5PR12MB6083:EE_ X-MS-Office365-Filtering-Correlation-Id: 53e9e063-6407-40f2-7ba4-08dee3e301b1 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|23010399003|376014|36860700016|7416014|10067099003|56012099006|11063799006|22082099003|18002099003; X-Microsoft-Antispam-Message-Info: LBId/1qYii6pq40tVMMunvKbpEEYhNvQncTGCznU/BYNG3Hrcx0BjLO9lZ9s6p3mOcerrGO+82RAskN7ZiScxcwEdTc19mEddy8tbMxHMJ/lc9QChkeIXtiuZ1HbC0UK/+nRAq3AGbgKu+xoSsKF9vNFeC4OaUBITPewKO97bSrGWV8d0Fr66k/F1KVs5c4k+TuQkPZsX1s6be6zEu+xC8LiYfhPMBRYAZHtdkEsADVCOYCprCsAtHBZzWblcHyRODKHcApRSs+Qg9q2RAjRcjSjRv0v90tELhlbHbzXhIGTPW2hK3LFj7Eok9f0gB+LFjP9GqMgkUFUlfrIHj8EoDKxs0D7PPngwWP5LJ7X8U7X7eZVcCbt+0uKdg0ENc0eMthZ4lHOAuh2E4ad1rJ976Q1NUzcZLtvk8cIKSXU1LlzwEVpnE8IzTN4qV1l7DlNPZIFMqsuSSWYE17PfPWwkElG+E4r7/oF7Pke/cMZGFuUK7p2ubw2AVee5MU7W19Jyt+6nrH1CkAhUtw2KJp0h0oSQ7rP9ae0NCHagDyncEQU7ZuSLCoDndzMAy/EB2aiZctfIHwOeKT+IEPlp1luTHegoEJTtPRnR6R1KvfwBHqTvf9BT41abdfepY4Iy7NrgrMzqmlhoCilPikJMn8nswJ883E9OiUTiKsPczZ5cktxyfDhvFGrWkhtzFAmK+LotCM5FeK419PyUf2ACQZHDw== X-Forefront-Antispam-Report: CIP:165.204.84.17;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:satlexmb08.amd.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(82310400026)(1800799024)(23010399003)(376014)(36860700016)(7416014)(10067099003)(56012099006)(11063799006)(22082099003)(18002099003);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: MHEZHm0jLwF923Tsa883v9cuvYNu60eibnMTTziQ8xbvNUBjjOIVT4ipEsbXQG6ljB12yIsjg+tXfZqLGBUV4LoOzyVj8dnpwkmiCRUIcL8P5fn52iOlbQcDoM1AIeC0U0ecNtdWBUzg23r+cr3sKvPPZf3djcPJQh1PKknjB4YGjiC8CZMIYC+qoPlW2GfiDfQoY1BqkJMmLs4Rq5G0E0e/KzESpdhKp23Ctxc9OYE0toor0NWiBJ5i0yLqyqfLAROE/i+5Fz4H9fF92S+ZVdheAqH+vT7a+/F2PVNQpYRSJ7RRNmm+B4AV0f1WpJcUHw42jD0F4Hv+HbNDQ0uw2zCmzwSyq5FRa04uOwUSIoXZRME9W3Jb5iO0Oam/QuAaDrBHyhe0GOyYqW1MADEir/Rnqn+WyU7+B2dMhku+ee29/u5gb0fhCgXJdzUkPcze X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Jul 2026 09:08:45.8041 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 53e9e063-6407-40f2-7ba4-08dee3e301b1 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb08.amd.com] X-MS-Exchange-CrossTenant-AuthSource: CY4PEPF0000EDD4.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY5PR12MB6083 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260717_020853_157354_D4D9F551 X-CRM114-Status: GOOD ( 13.04 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The MCDMA BD format differs between memory-to-device (MM2S) and device-to-memory (S2MM) directions, but the driver was using generic 'status' and 'sideband_status' fields for both. This led to incorrect residue calculations when the hardware updates direction-specific fields. Refactor the descriptor structure to use unions with direction-specific field mappings, and update the residue calculation logic to select the correct status field based on DMA direction. This matches the hardware descriptor layout and fixes incorrect residue reporting. Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support") Reviewed-by: Radhey Shyam Pandey Signed-off-by: Srinivas Neeli --- Changes in V5: - No change. Changes in V4: - Added Reviewed-by: Radhey Shyam Pandey. Changes in V3: - Renamed subject from "for MM2S vs S2MM" to "based on DMA direction". - Reworded commit message for clarity. - Added XILINX_MCDMA_BD_HW_SIZE macro and static_assert to verify descriptor size at compile time. - Refactored residue calculation to separate addition and subtraction operations for better readability. Changes in V2: - No change. --- drivers/dma/xilinx/xilinx_dma.c | 26 +++++++++++++++++++------- 1 file changed, 19 insertions(+), 7 deletions(-) diff --git a/drivers/dma/xilinx/xilinx_dma.c b/drivers/dma/xilinx/xilinx_dma.c index 98b41b8f8915..ff5b29a808e9 100644 --- a/drivers/dma/xilinx/xilinx_dma.c +++ b/drivers/dma/xilinx/xilinx_dma.c @@ -223,6 +223,7 @@ #define XILINX_MCDMA_IRQ_ERR_MASK BIT(7) #define XILINX_MCDMA_BD_EOP BIT(30) #define XILINX_MCDMA_BD_SOP BIT(31) +#define XILINX_MCDMA_BD_HW_SIZE 64 /** * struct xilinx_vdma_desc_hw - Hardware Descriptor @@ -277,8 +278,10 @@ struct xilinx_axidma_desc_hw { * @buf_addr_msb: MSB of Buffer address @0x0C * @rsvd: Reserved field @0x10 * @control: Control Information field @0x14 - * @status: Status field @0x18 - * @sideband_status: Status of sideband signals @0x1C + * @mm2s_ctrl_sideband: Sideband control info for mm2s @0x18 + * @s2mm_status: Status field for s2mm @0x18 + * @mm2s_status: Status field for mm2s @0x1C + * @s2mm_sideband_status: Sideband status for s2mm @0x1C * @app: APP Fields @0x20 - 0x30 */ struct xilinx_aximcdma_desc_hw { @@ -288,10 +291,17 @@ struct xilinx_aximcdma_desc_hw { u32 buf_addr_msb; u32 rsvd; u32 control; - u32 status; - u32 sideband_status; + union { + u32 mm2s_ctrl_sideband; + u32 s2mm_status; + }; + union { + u32 mm2s_status; + u32 s2mm_sideband_status; + }; u32 app[XILINX_DMA_NUM_APP_WORDS]; } __aligned(64); +static_assert(sizeof(struct xilinx_aximcdma_desc_hw) == XILINX_MCDMA_BD_HW_SIZE); /** * struct xilinx_cdma_desc_hw - Hardware Descriptor @@ -1015,9 +1025,11 @@ static u32 xilinx_dma_get_residue(struct xilinx_dma_chan *chan, struct xilinx_aximcdma_tx_segment, node); aximcdma_hw = &aximcdma_seg->hw; - residue += - (aximcdma_hw->control & chan->xdev->max_buffer_len) - - (aximcdma_hw->status & chan->xdev->max_buffer_len); + residue += aximcdma_hw->control & chan->xdev->max_buffer_len; + if (chan->direction == DMA_DEV_TO_MEM) + residue -= aximcdma_hw->s2mm_status & chan->xdev->max_buffer_len; + else + residue -= aximcdma_hw->mm2s_status & chan->xdev->max_buffer_len; } } -- 2.43.0