[RFC PATCH 0/2] drm/meson: add HDMI support for GXLX2

[Zinan Zhou <zinan@mieulab.com>]

This RFC adds HDMI transmitter support for the Amlogic GXLX2 family,
observed as an S905L3 (CPU major ID 0x2a) in a FiberHome HG680-LC set-top
box.

GXLX2 is unusual in that the display pipeline, clocks and HDMI PHY follow
the older GXL path, while the HDMI controller register interface is
directly mapped: DWC registers are byte-addressed from 0xda800000 and TOP
registers are 32-bit registers at 0xda808000 + index * 4. The existing
G12A access callbacks implement this layout, but using all G12A match data
would select the wrong PHY initialization for GXLX2.

Patch 1 proposes a dedicated amlogic,meson-gxlx2-dw-hdmi compatible
without a meson-gx-dw-hdmi fallback. Patch 2 adds dedicated match data
combining direct register callbacks with GXL PHY behavior. It also handles
the GXLX2 value for the 297 MHz PHY bucket and adds the compatible to the
Meson DRM component match list.

This RFC depends on the separately posted common Meson DW-HDMI regmap fix:

  drm/meson: constrain the DW-HDMI regmap range
  https://lore.kernel.org/all/20260718090710.70534-1-zinan@mieulab.com/

That formal bug-fix patch bounds register iteration below the directly
mapped TOP block and prevents the legacy 16-bit indirect interface from
wrapping. It is intentionally not part of this RFC so it can be reviewed
and merged without waiting for agreement on the GXLX2 DT ABI.

I would particularly appreciate feedback on two DT ABI questions:

1. Is amlogic,meson-gxlx2-dw-hdmi the appropriate block compatible name?
2. Should the DWC and TOP windows be represented as one contiguous MMIO
   resource, as in this RFC, or as two named resources?

Evidence and disclosure:

- The GXLX2 addresses and 297 MHz value are factual results of analysis of
  the HG680-LC vendor kernel. Firmware SHA-256 and focused behavioral
  evidence can be supplied if useful, but no firmware, kallsyms dump or
  disassembly is part of this submission.
- Public Amlogic-derived GPL source documents the ordinary GXL 2.97 Gbps
  values and public GPL-2.0+/MIT source documents the same direct DWC/TOP
  access mechanism used on later SoCs. The implementation here does not
  copy a vendor function body.

Testing:

- An equivalent Linux 6.6.18 implementation boots from eMMC on the
  HG680-LC.
- 1920x1080 HDMI video was physically verified on an LG 27GL850.
- Two-channel HDMI LPCM through the display and analog stereo audio were
  physically verified.
- The downstream 6.12 port boots from eMMC with working Ethernet/SSH and
  has physically verified 1920x1080@60 video and HDMI LPCM.
- With the generic Meson non-CEA mode-range change already present in
  current mainline, 2560x1440@59.95 video and HDMI LPCM were physically
  verified on the display's native timing.
- The RFC port builds on arm64 and its binding passes dt_binding_check.
- 3840x2160 at 30 Hz has not yet been physically tested. That test is
  required before a non-RFC PATCH v1 because it exercises the
  GXLX2-specific 297 MHz branch. It is not a blocker for the verified
  1080p/1440p use case.
- No other GXLX2 board has been tested yet.

The initial RFC intentionally contains no board DTS. A downstream-only
HG680-LC DTS is being kept as DO NOT MERGE until the compatible and resource
model have received initial feedback.

Assisted-by: Codex:gpt-5.6-sol

Zinan Zhou (2):
  dt-bindings: display: meson-dw-hdmi: add GXLX2 compatible
  drm/meson: add GXLX2 HDMI register support

 .../display/amlogic,meson-dw-hdmi.yaml        |  7 ++--
 drivers/gpu/drm/meson/meson_drv.c             |  1 +
 drivers/gpu/drm/meson/meson_dw_hdmi.c         | 33 ++++++++++++++++---
 3 files changed, 34 insertions(+), 7 deletions(-)


base-commit: b0a652436b892eb9a036a031b33099dca036faaa
prerequisite-patch-id: 0a689485bbc3c1d77d52aeee0b81e4943d1e904a
-- 
2.43.0