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Sat, 18 Jul 2026 17:48:14 -0700 (PDT) Received: from [127.0.0.2] ([185.213.155.231]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-c1712a62e79sm270250066b.30.2026.07.18.17.48.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Jul 2026 17:48:14 -0700 (PDT) From: Michal Gorlas Date: Sun, 19 Jul 2026 02:47:54 +0200 Subject: [PATCH] PCI: imx6: enable ASPM L1 only iff CLKREQ# is supported MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260719-l1-conditional-imx-v1-1-a55a57915c68@9elements.com> X-B4-Tracking: v=1; b=H4sIALkeXGoC/yXMywrDIBCF4VcJs86AGnqhr1Ky8DJpp1gtaosgv ntsu/zgnL9BpsSU4TI1SPThzDEMyHkCe9fhRshuGJRQR3GSC3qJNgbHZQy1R35WtMpsTglN4ny AcXwl2rj+otf17/w2D7LlW4Led1B9dBB2AAAA X-Change-ID: 20260713-l1-conditional-imx-c2bfd20ae085 To: Richard Zhu , Lucas Stach , Lorenzo Pieralisi , =?utf-8?q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Cc: linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org X-Mailer: b4 0.15.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=B4EB74EA41969D1140A4D1791596726986433F8C X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260718_174819_038057_54621C1F X-CRM114-Status: GOOD ( 14.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms"), ASPM states are force enabled on all devicetree platforms. This causes PCI devices on some iMX SoCs (for e.g. iMX 8M Plus Kontron SMARC eval carrier) to enter L1 even though CLKREQ# is not supported (and consequently supports-clkreq is not set in pcie controller node of their DT), which causes the device to never wake up from L1. Hence, disable L1 capability in the LINKCAP register if supports-clkreq is not set in the DT explicitly. Note, the logic here is very similar to 613f3255a35a, only difference is that leaving L0s enabled does not cause issues (at least I never encountered them myself when testing on the device) as its not dependent on CLKREQ# being physically there. Since there is already a way of specifying its presence in the DT, the driver should be aware and disable L1. Fixes: f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM states for devicetree platforms") Signed-off-by: Michal Gorlas --- drivers/pci/controller/dwc/pci-imx6.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c index 98e1db751132..7471501fbf04 100644 --- a/drivers/pci/controller/dwc/pci-imx6.c +++ b/drivers/pci/controller/dwc/pci-imx6.c @@ -1318,6 +1318,22 @@ static void imx_pcie_assert_perst(struct imx_pcie *imx_pcie, bool assert) } } +static void imx_pcie_disable_l1(struct dw_pcie *pci) +{ + u32 val; + u8 offset; + + offset = dw_pcie_find_capability(pci, PCI_CAP_ID_EXP); + + dw_pcie_dbi_ro_wr_en(pci); + + val = dw_pcie_readl_dbi(pci, offset + PCI_EXP_LNKCAP); + val &= ~PCI_EXP_LNKCAP_ASPM_L1; + dw_pcie_writel_dbi(pci, offset + PCI_EXP_LNKCAP, val); + + dw_pcie_dbi_ro_wr_dis(pci); +} + static int imx_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci = to_dw_pcie_from_pp(pp); @@ -1442,6 +1458,9 @@ static int imx_pcie_host_init(struct dw_pcie_rp *pp) imx_setup_phy_mpll(imx_pcie); + if (!imx_pcie->supports_clkreq) + imx_pcie_disable_l1(pci); + return 0; err_phy_off: --- base-commit: a13c140cc289c0b7b3770bce5b3ad42ab35074aa change-id: 20260713-l1-conditional-imx-c2bfd20ae085 Best regards, -- Michal Gorlas