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Sun, 19 Jul 2026 14:13:42 -0700 (PDT) Received: from localhost.localdomain ([2a0d:3344:2841:7708:a101:2b8a:f76:a00f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49549a3e2a9sm224108815e9.4.2026.07.19.14.13.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jul 2026 14:13:42 -0700 (PDT) From: =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Brian Masney , Andre Przywara , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= Subject: [PATCH v1 0/4] clk: sunxi-ng: fix the A523/T527 GPU clock model, enable GPU DVFS Date: Sun, 19 Jul 2026 23:13:15 +0200 Message-ID: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260719_141345_169523_900CC16C X-CRM114-Status: GOOD ( 15.07 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org This series follows up on the discussion in [1], where Chen-Yu pointed out that the A523/T527 GPU mod clock is not a standard divider but a fractional one: GPU_CLK = Clock Source * ((16-M)/16), with M 0-15. I checked this against the T527 user manual (v0.92, section 2.7.6.58, "FACTOR_M: mask M cycles at 16 cycles") and verified it on hardware: with the current linear model, forcing each OPP on an Orange Pi 4A and measuring the real GPU frequency with the Mali cycle counter gives OPP request programmed measured 150 MHz 600M, M=3 ~487 MHz 200 MHz 800M, M=3 648 MHz 300 MHz 600M, M=1 560 MHz 400 MHz 800M, M=1 749 MHz 600 MHz 600M, M=0 599 MHz so every OPP below 600 MHz silently overclocks, up to 25% above the vendor ceiling, and thermal throttling to "400 MHz" actually raises the GPU frequency. Patch 1 adds a small ccu type implementing the cycle-masking semantics. Patch 2 switches the A523 GPU clock to it, drops pll-periph0-800M from the selectable parents (the vendor BSP removed it citing GPU job faults) and drops CLK_SET_RATE_PARENT (pll-gpu loses its CLK_SET_RATE_GATE protection once the GPU runs from a periph output). Patch 3 registers the existing sunxi-ng mux notifier so the GPU is parked on pll-periph0-600M while pll-gpu changes rate, as Chen-Yu suggested in the same thread. Patch 4 adds the BSP operating points to the Orange Pi 4A DT, which enables panfrost devfreq. With the series applied the same cycle-counter measurement reads 149/199/300/399/597 MHz for the five OPPs, all from the intended parents, and devfreq scaling plus thermal throttling (emulated temperature) behave correctly under load. The higher speed-bin operating points of the BSP (648-792 MHz, gated by a SID efuse bin, running from pll-gpu) are left for a follow-up. [1] https://lore.kernel.org/linux-sunxi/20260719153122.892013-1-juanmanuellopezcarrillo@gmail.com/ Juan Manuel López Carrillo (4): clk: sunxi-ng: add cycle-masking divider (maskdiv) clock type clk: sunxi-ng: sun55i-a523: GPU clock divider is fractional, not linear clk: sunxi-ng: sun55i-a523: reparent GPU while pll-gpu changes rate arm64: dts: allwinner: t527-orangepi-4a: add GPU OPP table .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 30 +++ drivers/clk/sunxi-ng/Makefile | 1 + drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 47 ++++- drivers/clk/sunxi-ng/ccu_maskdiv.c | 199 ++++++++++++++++++ drivers/clk/sunxi-ng/ccu_maskdiv.h | 71 +++++++ 5 files changed, 342 insertions(+), 6 deletions(-) create mode 100644 drivers/clk/sunxi-ng/ccu_maskdiv.c create mode 100644 drivers/clk/sunxi-ng/ccu_maskdiv.h -- 2.47.3