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Sun, 19 Jul 2026 14:13:51 -0700 (PDT) Received: from localhost.localdomain ([2a0d:3344:2841:7708:a101:2b8a:f76:a00f]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49549a3e2a9sm224108815e9.4.2026.07.19.14.13.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 19 Jul 2026 14:13:51 -0700 (PDT) From: =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= To: Michael Turquette , Stephen Boyd , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Brian Masney , Andre Przywara , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= Subject: [PATCH v1 4/4] arm64: dts: allwinner: t527-orangepi-4a: add GPU OPP table Date: Sun, 19 Jul 2026 23:13:19 +0200 Message-ID: <20260719211319.982285-5-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> References: <20260719211319.982285-1-juanmanuellopezcarrillo@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260719_141353_453770_FC4B3DBE X-CRM114-Status: GOOD ( 12.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the Mali-G57 operating points from the vendor BSP universal table (150/200/300/400/600 MHz) so panfrost devfreq can scale the GPU instead of running at the boot clock. All operating points use 920 mV: the BSP table specifies 900 mV for every universal OPP, but on this board the GPU rail (AXP717 DCDC2, vdd-gpu-sys) is a fixed 920 mV supply, so the OPP voltage states the actual rail value and voltage transitions are no-ops. The higher speed-bin points of the BSP (648-792 MHz) are not included: they are gated by a SID efuse bin and need pll-gpu as a live parent. Depends on the sun55i-a523 GPU clock divider fix (the OPP rates are only produced correctly with the cycle-masking divider model); validated on hardware with the Mali cycle counter: 149/199/300/399/597 MHz measured under load, thermal-emulation throttling included. Signed-off-by: Juan Manuel López Carrillo --- .../dts/allwinner/sun55i-t527-orangepi-4a.dts | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts index 055be86e5..0fd73a1bb 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-orangepi-4a.dts @@ -30,6 +30,35 @@ ext_osc32k: ext-osc32k-clk { clock-output-names = "ext_osc32k"; }; + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <920000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <920000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <920000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <920000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <920000>; + }; + }; + leds { compatible = "gpio-leds"; @@ -116,6 +145,7 @@ &gmac1 { &gpu { mali-supply = <®_dcdc2>; + operating-points-v2 = <&gpu_opp_table>; status = "okay"; }; -- 2.47.3