From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id F0FF6C44525 for ; Mon, 20 Jul 2026 05:15:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Type: Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date :Subject:Cc:To:From:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=n3e/3Mz+2j77ICnsCAepz9q/sEHFkYkcB3C4JHFJ/B8=; b=dNhFN4TI/Qm7Lh2IMWXcwYD5o1 0vruLi+K9NEe2TuyRpHeOt6OZrU6sW3LAwBgFy5AiAQLLiaEBoeeHtAYgR/b1W/l6sCg9Pkci7RZf nQ8ki36dVQzGDN3gQIks7u2Ict5NW5cyf5RkFKXRdFJoZZMyR2uS70SjWqs7hlhX9Zw3KoO16DhE2 Gb3/qXYnTqOoemfsdcf8+PV/UHDO6/UKsMarhQVQG7Jpn7BTpOV8MMgHGM84+OQMDzyxT1E2OGxVk q/B32oXWAl+Q9j0tGIxyq1QcXHLZ5BWZlrms+QZzrOPKQNvZ96PeR8GNpw+WS7BnbpddpAsqEddJq JMkvK2KA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wlgLg-00000005qbl-1mqV; Mon, 20 Jul 2026 05:15:28 +0000 Received: from mail-japaneastazlp170120005.outbound.protection.outlook.com ([2a01:111:f403:c405::5] helo=TYPPR03CU001.outbound.protection.outlook.com) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wlgLZ-00000005qYj-3fAi for linux-arm-kernel@lists.infradead.org; Mon, 20 Jul 2026 05:15:23 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector10001; d=microsoft.com; cv=none; b=Ntxvo5qgbLpt3yXlpG2LB1afLlBHygN1TrSR9aI79jpwqUCXElbcGOA59P7d0/3ARrh/kIHjkQcP05QmVXaJkqQo4AmuMYaCIqLWWzR2US7UJHv9amJ14vAX2i5sgcAumIfSfE/XYn5+Hnr1DBviJrDWF8PSOB972S6ENa8S0bUlhitl0M8sz4KDI5SkB+mC+7ELQZVlWAXDpsHv1JhlMR3oAwqPX3enWf7ZvtFpdqUEpmOsf3ffjNEChjcie5TKCft9by9jRjKeyaMT8ZcMwlurWkxa+sxnvFQTT3Eza/846qrTTPUWj4W6UHZ59VY0GQfldL31ym/VoamsY+6PWQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector10001; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-AntiSpam-MessageData-ChunkCount:X-MS-Exchange-AntiSpam-MessageData-0:X-MS-Exchange-AntiSpam-MessageData-1; bh=n3e/3Mz+2j77ICnsCAepz9q/sEHFkYkcB3C4JHFJ/B8=; b=jDnRcYp91yi5Y1vYnIJi2dQGw9dCqmgVcEprD2UqNjpJ3+hJuYYJ4qEQY7AUsbzBwzIM0pl1y9nrWY+CEqYj+SgPeg18jPI2dGEsPE5aG+G0MlEXLaRtyqHDnWW7GQxKj5H2M8XKSjZqwu3VeItC0N2q6oeIgqtP5opjF9G23GhpMfYd169XZ+QLYnCh9ew098zwkpMC/FIxf+/QL/b8HI99Kqy6NYJHUV/MIxBSevAx7vu2PJ8kgq0EAhuCtedtUVgp5Uhi82aM0iRSTFx44K/tz7P+Jxuqse2cAoC1Q69nVbzh4WynYx5qS2cx6EZ9ZM5EGtLA/JFw/y+j/kNRsw== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 222.71.101.198) smtp.rcpttodomain=baylibre.com smtp.mailfrom=cixtech.com; dmarc=bestguesspass action=none header.from=cixtech.com; dkim=none (message not signed); arc=none (0) Received: from PS2PR02CA0055.apcprd02.prod.outlook.com (2603:1096:300:5a::19) by TYZPR06MB5228.apcprd06.prod.outlook.com (2603:1096:400:1fd::10) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.223.16; Mon, 20 Jul 2026 05:15:10 +0000 Received: from TY2PEPF0000AB84.apcprd03.prod.outlook.com (2603:1096:300:5a:cafe::7d) by PS2PR02CA0055.outlook.office365.com (2603:1096:300:5a::19) with Microsoft SMTP Server (version=TLS1_3, cipher=TLS_AES_256_GCM_SHA384) id 15.21.223.16 via Frontend Transport; Mon, 20 Jul 2026 05:15:10 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 222.71.101.198) smtp.mailfrom=cixtech.com; dkim=none (message not signed) header.d=none;dmarc=bestguesspass action=none header.from=cixtech.com; Received-SPF: Pass (protection.outlook.com: domain of cixtech.com designates 222.71.101.198 as permitted sender) receiver=protection.outlook.com; client-ip=222.71.101.198; helo=smtprelay.cixcomputing.com; pr=C Received: from smtprelay.cixcomputing.com (222.71.101.198) by TY2PEPF0000AB84.mail.protection.outlook.com (10.167.253.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Mon, 20 Jul 2026 05:15:09 +0000 Received: from cix (unknown [172.18.64.61]) by smtprelay.cixcomputing.com (Postfix) with ESMTPSA id 75B81427CEF1; Mon, 20 Jul 2026 13:15:08 +0800 (CST) From: joakim.zhang@cixtech.com To: mturquette@baylibre.com, sboyd@kernel.org, bmasney@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, p.zabel@pengutronix.de Cc: cix-kernel-upstream@cixtech.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Joakim Zhang , Krzysztof Kozlowski Subject: [PATCH v10 1/4] dt-bindings: soc: cix: add sky1 audss cru controller Date: Mon, 20 Jul 2026 13:15:02 +0800 Message-ID: <20260720051505.1252774-2-joakim.zhang@cixtech.com> X-Mailer: git-send-email 2.50.1 In-Reply-To: <20260720051505.1252774-1-joakim.zhang@cixtech.com> References: <20260720051505.1252774-1-joakim.zhang@cixtech.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB84:EE_|TYZPR06MB5228:EE_ Content-Type: text/plain X-MS-Office365-Filtering-Correlation-Id: da0453f7-3b6c-4a78-7fe0-08dee61ddec0 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|82310400026|36860700016|7416014|376014|1800799024|3023799007|6133799003|10067099003|56012099006|18002099003|22082099003; X-Microsoft-Antispam-Message-Info: v6+ucvw3FCKd64smSOowkquUyq8SxmnyBKKIHroEj440a/QFSwd4CWZd4/tTjnSdj7DQBAB93qtR1aMqwVrK0DdwKonRSosgjztPa/9nbCayf3mPRYeoWZ9bRBF6HgWrBZvkhtMU+I+bPUxwT7OPa7K/chIuRQ6ceHLijUheuIW6HeTW7FFaUkM4SbmmP9f1765ODooQFSGT744VTy+L4CxPoETAyDn+ZhuZ/awv0XKskbIcGcmmHe/+2mpkSzLbcS5MEPc6NVuXn/ChPDfJ3qa6ng8trApl5rECAVuC7eDPW7g2kq7yw3hMb6YVO0reW8sKDXUPNuBhnrhn7s/JJkkq02iqyemVyQ0yCCZgFjIbnXTTeu28mquh242YFIB0M+nRW2ywCNljvfqyzdEPbkeF1J6DBhQW9u6na5ASOU4daCAsfKeHRa+DBKPyWHsDx86lAlpVtRkzad3FmbBA1cpZA6ueS42SyyZd7m0q3H+CzYypcPOO5NqhHI6KYr1/X5ZJIVd09msjEb9m1D1nYuspYHmBPvyuZZol7BLV8nyCpnOtR3dc8GiXvJKFE3PEHosReSOnEemlofJOnHkH4yRmWeDOHO5izsjsbYdSPC4MEiabhwzE3I6l0TafawDJM530gKBvX66EETP5ZcV/Zg== X-Forefront-Antispam-Report: CIP:222.71.101.198;CTRY:CN;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:smtprelay.cixcomputing.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(13230040)(23010399003)(82310400026)(36860700016)(7416014)(376014)(1800799024)(3023799007)(6133799003)(10067099003)(56012099006)(18002099003)(22082099003);DIR:OUT;SFP:1102; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: bKVLN3nWg/BWy0D5HbAO4FTft0RIBxWTYGAJsLZOtLs+VjxmfV5pTecUYdK8SOjZwMvgbZo9EBCRHyQAcKXkucIy+xjiYNsBMSC5O2qW1f3quvKOeuSIGfk4xciyTd6ijNbPFaoOEideQmYqDoid8aKY48zbDV8xVJe6PIyZKHQ4l1uOHXcIwV2xJFaaX7DrtzNXn4OhalSCpUlPyXvJzbcQNcgoPqrLiMQN+VoANO7VKMbOYiw0pNOFBT0y2pnkcpp4A3vQLfH8rVSTeZYzbtwLOlE1Ih5lTnnyMlj5yEPDtfjpmk9CFNoq+SxM0ulAjxI732+a4Oh1OwR5AOrr2dCIpJHKrriAtbx4bc1fa9W7iBJeBbE8iG6BIkQWnK4K9oCdsuAKr6VtB9b0/e8+hpt/HqavZi0jGytE+Ubt9VzSuNSLZ6RBvmo8s3ZsIa6f X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 20 Jul 2026 05:15:09.6516 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: da0453f7-3b6c-4a78-7fe0-08dee61ddec0 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB84.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYZPR06MB5228 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260719_221521_920840_0B8F98DF X-CRM114-Status: GOOD ( 13.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Joakim Zhang The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU) groups clock muxing, gating and block-level software reset control in a single register block. Reviewed-by: Krzysztof Kozlowski Signed-off-by: Joakim Zhang --- .../bindings/soc/cix/cix,sky1-audss-cru.yaml | 92 +++++++++++++++++++ .../dt-bindings/clock/cix,sky1-audss-cru.h | 60 ++++++++++++ .../dt-bindings/reset/cix,sky1-audss-cru.h | 25 +++++ 3 files changed, 177 insertions(+) create mode 100644 Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml create mode 100644 include/dt-bindings/clock/cix,sky1-audss-cru.h create mode 100644 include/dt-bindings/reset/cix,sky1-audss-cru.h diff --git a/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml b/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml new file mode 100644 index 000000000000..50dd0593e1d9 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/cix/cix,sky1-audss-cru.yaml @@ -0,0 +1,92 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/cix/cix,sky1-audss-cru.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cix Sky1 audio subsystem clock and reset unit + +maintainers: + - Joakim Zhang + +description: | + The Cix Sky1 Audio Subsystem (AUDSS) Clock and Reset Unit (CRU) groups + audio-related clock muxing, gating and block-level software reset control + in a single register block. + + A single device node exposes both the clock controller and software reset + lines. The clock driver registers as a platform driver; the reset controller + is registered by an auxiliary driver bound from the clock driver. + + Four SoC-level reference clocks listed in clocks/clock-names feed the AUDSS + clock tree. Internal AUDSS clocks are exposed via #clock-cells; indices are + defined in include/dt-bindings/clock/cix,sky1-audss-cru.h. + + Block-level software reset indices are exposed via #reset-cells; indices + are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h. + + The SoC syscon NoC (or bus) reset is described via resets. The audio + subsystem power domain is described via power-domains. + +properties: + compatible: + const: cix,sky1-audss-cru + + reg: + maxItems: 1 + + '#clock-cells': + const: 1 + description: + Clock indices are defined in include/dt-bindings/clock/cix,sky1-audss-cru.h. + + '#reset-cells': + const: 1 + description: + Reset indices are defined in include/dt-bindings/reset/cix,sky1-audss-cru.h. + + clocks: + items: + - description: I2S parent clock for sampling rates multiple of 8kHz. + - description: I2S parent clock for sampling rates multiple of 11.025kHz. + - description: Clock feeding most devices in AUDSS (NOC, DSP, SRAM, HDA, DMAC, I2S, and mailbox). + - description: Clock feeding HDA, timer and watchdog, which is a dedicated 48 MHz clock. + + clock-names: + items: + - const: x8k + - const: x11k + - const: sys + - const: 48m + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + +required: + - compatible + - reg + - '#clock-cells' + - '#reset-cells' + - clocks + - clock-names + - power-domains + - resets + +additionalProperties: false + +examples: + - | + audss_cru: clock-controller@7110000 { + compatible = "cix,sky1-audss-cru"; + reg = <0x7110000 0x10000>; + #clock-cells = <1>; + #reset-cells = <1>; + clocks = <&scmi_clk 76>, <&scmi_clk 78>, + <&scmi_clk 70>, <&scmi_clk 71>; + clock-names = "x8k", "x11k", "sys", "48m"; + power-domains = <&smc_devpd 0>; + resets = <&s5_syscon 31>; + }; diff --git a/include/dt-bindings/clock/cix,sky1-audss-cru.h b/include/dt-bindings/clock/cix,sky1-audss-cru.h new file mode 100644 index 000000000000..8c58ef8bf682 --- /dev/null +++ b/include/dt-bindings/clock/cix,sky1-audss-cru.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ + +#ifndef _DT_BINDINGS_CLOCK_CIX_SKY1_AUDSS_CRU_H +#define _DT_BINDINGS_CLOCK_CIX_SKY1_AUDSS_CRU_H + +#define CLK_AUD_CLK4_DIV2 0 +#define CLK_AUD_CLK4_DIV4 1 +#define CLK_AUD_CLK5_DIV2 2 + +#define CLK_DSP_CLK 3 +#define CLK_DSP_BCLK 4 +#define CLK_DSP_PBCLK 5 + +#define CLK_SRAM_AXI 6 + +#define CLK_HDA_SYS 7 +#define CLK_HDA_HDA 8 + +#define CLK_DMAC_AXI 9 + +#define CLK_WDG_APB 10 +#define CLK_WDG_WDG 11 + +#define CLK_TIMER_APB 12 +#define CLK_TIMER_TIMER 13 + +#define CLK_MB_0_APB 14 /* MB0: ap->dsp */ +#define CLK_MB_1_APB 15 /* MB1: dsp->ap */ + +#define CLK_I2S0_APB 16 +#define CLK_I2S1_APB 17 +#define CLK_I2S2_APB 18 +#define CLK_I2S3_APB 19 +#define CLK_I2S4_APB 20 +#define CLK_I2S5_APB 21 +#define CLK_I2S6_APB 22 +#define CLK_I2S7_APB 23 +#define CLK_I2S8_APB 24 +#define CLK_I2S9_APB 25 +#define CLK_I2S0 26 +#define CLK_I2S1 27 +#define CLK_I2S2 28 +#define CLK_I2S3 29 +#define CLK_I2S4 30 +#define CLK_I2S5 31 +#define CLK_I2S6 32 +#define CLK_I2S7 33 +#define CLK_I2S8 34 +#define CLK_I2S9 35 + +#define CLK_MCLK0 36 +#define CLK_MCLK1 37 +#define CLK_MCLK2 38 +#define CLK_MCLK3 39 +#define CLK_MCLK4 40 + +#endif diff --git a/include/dt-bindings/reset/cix,sky1-audss-cru.h b/include/dt-bindings/reset/cix,sky1-audss-cru.h new file mode 100644 index 000000000000..55e9f3797b30 --- /dev/null +++ b/include/dt-bindings/reset/cix,sky1-audss-cru.h @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2026 Cix Technology Group Co., Ltd. + */ +#ifndef DT_BINDINGS_RESET_CIX_SKY1_AUDSS_CRU_H +#define DT_BINDINGS_RESET_CIX_SKY1_AUDSS_CRU_H + +#define AUDSS_I2S0_SW_RST 0 +#define AUDSS_I2S1_SW_RST 1 +#define AUDSS_I2S2_SW_RST 2 +#define AUDSS_I2S3_SW_RST 3 +#define AUDSS_I2S4_SW_RST 4 +#define AUDSS_I2S5_SW_RST 5 +#define AUDSS_I2S6_SW_RST 6 +#define AUDSS_I2S7_SW_RST 7 +#define AUDSS_I2S8_SW_RST 8 +#define AUDSS_I2S9_SW_RST 9 +#define AUDSS_WDT_SW_RST 10 +#define AUDSS_TIMER_SW_RST 11 +#define AUDSS_MB0_SW_RST 12 +#define AUDSS_MB1_SW_RST 13 +#define AUDSS_HDA_SW_RST 14 +#define AUDSS_DMAC_SW_RST 15 + +#endif -- 2.50.1