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[93.144.65.248]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-495653c98ebsm126602615e9.13.2026.07.22.03.42.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 22 Jul 2026 03:42:05 -0700 (PDT) From: Stefano Radaelli X-Google-Original-From: Stefano Radaelli To: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Cc: pierluigi.p@variscite.com, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam Subject: [PATCH v1 1/1] arm64: dts: imx8qm-ss-dma: add LPUART4 Date: Wed, 22 Jul 2026 12:42:00 +0200 Message-ID: <20260722104200.17729-1-stefano.r@variscite.com> X-Mailer: git-send-email 2.47.3 MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260722_034208_182113_784CF1EF X-CRM114-Status: GOOD ( 10.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Stefano Radaelli Add the missing LPUART4 node to the i.MX8QM DMA subsystem description. The peripheral is present in the SoC and its LPCG clock controller is already described, but the UART device node is currently missing. Describe its registers, interrupt, clocks, power domain and eDMA channels based on the NXP downstream device tree. Signed-off-by: Stefano Radaelli --- arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi index 974e193f8dcb..25c5e4423163 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-dma.dtsi @@ -8,6 +8,22 @@ /delete-node/ &adma_pwm_lpcg; &dma_subsys { + lpuart4: serial@5a0a0000 { + compatible = "fsl,imx8qm-lpuart", "fsl,imx8qxp-lpuart"; + reg = <0x5a0a0000 0x1000>; + interrupts = ; + interrupt-parent = <&gic>; + clocks = <&uart4_lpcg 1>, <&uart4_lpcg 0>; + clock-names = "ipg", "baud"; + assigned-clocks = <&clk IMX_SC_R_UART_4 IMX_SC_PM_CLK_PER>; + assigned-clock-rates = <80000000>; + power-domains = <&pd IMX_SC_R_UART_4>; + dma-names = "rx","tx"; + dmas = <&edma2 20 0 1>, + <&edma2 21 0 0>; + status = "disabled"; + }; + uart4_lpcg: clock-controller@5a4a0000 { compatible = "fsl,imx8qxp-lpcg"; reg = <0x5a4a0000 0x10000>; -- 2.47.3