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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by DS1PEPF00017096.mail.protection.outlook.com (10.167.18.100) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.245.5 via Frontend Transport; Wed, 22 Jul 2026 12:57:28 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.45; Wed, 22 Jul 2026 05:57:13 -0700 Received: from moonraker.home (10.126.231.37) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Wed, 22 Jul 2026 05:57:11 -0700 From: Jon Hunter To: Mark Rutland , Marc Zyngier , "Daniel Lezcano" , Thomas Gleixner CC: , , , Jon Hunter Subject: [PATCH] clocksource/drivers/arm_arch_timer: Mark EL2 virtual timer broken for Tegra194/234 Date: Wed, 22 Jul 2026 13:56:51 +0100 Message-ID: <20260722125651.148595-1-jonathanh@nvidia.com> X-Mailer: git-send-email 2.43.0 MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: 8bit Content-Type: text/plain X-Originating-IP: [10.126.231.37] X-ClientProxiedBy: rnnvmail203.nvidia.com (10.129.68.9) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017096:EE_|IA0PPF7D094C5BF:EE_ X-MS-Office365-Filtering-Correlation-Id: 5e4f42e4-4d5c-46ca-6332-08dee7f0c950 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|36860700016|82310400026|5023799004|11063799006|10067099003|56012099006|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 3SchrC4BNWLUowUqE7dNpQ6cgflPSzac0gDYrfVhrFhGaRHdZWs+ghsU19CqoB00dpZiMFvu40bMfriv6bhoKxzSbLgi9NLjaNmRMZ+mO0p6YZDH+L3LcgRLTXC1hRk5QbPTfkat2nGCDFQzi9bV0zYcnmHfs4ktW3g27mZKOwkfqMYbXddnUhMpXps4+AMo7EnfDHm/PviIclodP8i/MkWf5PvvxaV7Rv9DXJ/b4JMRxx3o5lR2r/9fF47a05lwq1gGafTSodEQ89bYLovd8UpoHXcbCJgh2L9P+3dBE2udfyUBKAeAGQWVAM4m5Ago0bcLjtZ8tr/pirh1f0UcKoBTX5qjVvXNSMlE8yfRJBSbYwA6KtHF+sZULy7c5vgF9iH6LQMpNTvINMVkyviY4sR1sejQRj0tPXGNZRYio4rU10y8XTySzv697F/WVFFo X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 22 Jul 2026 12:57:28.7331 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5e4f42e4-4d5c-46ca-6332-08dee7f0c950 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017096.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA0PPF7D094C5BF X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260722_055738_622260_D97CE142 X-CRM114-Status: GOOD ( 14.00 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org The following warning is being observed on Tegra194 and Tegra234 platforms ... arch_timer: [Firmware Bug]: VHE-capable CPU without EL2 virtual timer interrupt Adding the missing EL2 virtual timer in device-tree for Tegra194 and Tegra234 is causing boot issues for both devices. The Tegra194 device includes a GIC-400 which defines PPIs for sec-phys, phys, virt and hyp-phys timer interrupts (per the dt-binding arm,arch_timer.yaml) but there is no PPI hyp-virt (EL2 virtual) timer and hence this is not supported for this device. The Tegra234 device does have a PPI for the EL2 virtual timer, but during CPU idle transitions into low-power states this timer is not preserved currently by firmware and hence causes boot issues when CPU idle is enabled. Avoid the warning for Tegra194 and Tegra234 devices by marking the EL2 virtual timer as broken. Suggested-by: Marc Zyngier Signed-off-by: Jon Hunter --- drivers/clocksource/arm_arch_timer.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/drivers/clocksource/arm_arch_timer.c b/drivers/clocksource/arm_arch_timer.c index 4adf756423de..b9ccb560ff8f 100644 --- a/drivers/clocksource/arm_arch_timer.c +++ b/drivers/clocksource/arm_arch_timer.c @@ -1090,6 +1090,17 @@ static int __init arch_timer_common_init(void) return arch_timer_arch_init(); } +static bool __init has_broken_el2_vtimer(void) +{ + static const char * const broken_el2_vtimer[] __initconst = { + "nvidia,tegra194", + "nvidia,tegra234", + NULL + }; + + return of_machine_compatible_match(broken_el2_vtimer); +} + /** * arch_timer_select_ppi() - Select suitable PPI for the current system. * @@ -1115,6 +1126,9 @@ static int __init arch_timer_common_init(void) static enum arch_timer_ppi_nr __init arch_timer_select_ppi(void) { if (is_kernel_in_hyp_mode()) { + if (has_broken_el2_vtimer()) + return ARCH_TIMER_HYP_PPI; + if (arch_timer_ppi[ARCH_TIMER_HYP_VIRT_PPI]) return ARCH_TIMER_HYP_VIRT_PPI; -- 2.43.0