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Tue, 28 Jul 2026 00:25:58 -0500 From: K Prateek Nayak To: Arnd Bergmann , Thomas Gleixner , "Ingo Molnar" , Peter Zijlstra , "Sebastian Andrzej Siewior" , Charlie Jenkins , Borislav Petkov , Dave Hansen , , Catalin Marinas , Will Deacon , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Heiko Carstens , Vasily Gorbik , Alexander Gordeev CC: Darren Hart , Davidlohr Bueso , =?UTF-8?q?Andr=C3=A9=20Almeida?= , , , , , , K Prateek Nayak , "H. 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More information can be found on v2 at https://lore.kernel.org/lkml/20260316052401.18910-1-kprateek.nayak@amd.com/ Notable changes in v5 ===================== Intel test robot flagged a case of compilers re-ordering the runtime_const usage before their initialization in futex_init() at https://lore.kernel.org/lkml/202607091538.58e3f39-lkp@intel.com/. This was fixed by adding a barrier() after the runtime_const_init() bits in futex_init() to prevent this re-ordering. Sashiko flagged that __fls(val), when val is 0, can be optimized by the compiler to consider val as non-zero and silently optimize the BUG_ON(!val && ...) to only consider the latter bits, skipping the !val check. Fix this by explicitly checking val before __fls(). Testing ======= Apart from x86, which was build and boot tested on baremetal, all the other architectures have been build and boot tested with cross-compile + QEMU with some light sanity testing on each. Patches are based on: git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git master at commit 8d0b0ef04514 ("Merge branch into tip/master: 'x86/tdx'") (27-07-2026) Diffstat from v5 is essentially 5+++++-- with effectively 3 lines of code change and 2 newlines; Resending for convenience since adding parital diffs to v5 was getting too finnicky and this is easier for pickup. Charlie's optimization for RISC-V bits to patch slli + srli with andi + nop if mask fits the immediate encoding is left to a later series once this is merged. (https://lore.kernel.org/lkml/178366995930.1208691.2993932866462893112.b4-review@b4/) Few comments from checkpatch.pl have been ignored to adhere to the style of the particular file. If something needs addressing, please let me know and I'll address it with a v6.X fixups unless there is a larger change that will require a re-spin Everyone has been Cc'd on the cover-letter and the futex bits for the context. Respective arch maintainers, reviewers, and whoever got lucky with get_maintainer.pl have been Cc'd on their respective arch specific changes. Futex maintainers and the lists will be receiving the whole series (sorry in advance!) --- changelog v5..v6: o Added a barrier after runtime_const_init() to prevent compilers from re-ordering their access before the initialization in futex_init(). (Sashiko, Intel test robot) o Added a zero check before __fls() to prevent smart compiler optimizations of a later BUG_ON(). (Sashiko) o Picked up Peter's S-o-b from his tree. o Collected tags from Charlie. (Thanks a ton!) o Rebased on latest tip. v5: https://lore.kernel.org/lkml/20260630045531.3939-1-kprateek.nayak@amd.com/ --- K Prateek Nayak (5): arm64/runtime-const: Use aarch64_insn_patch_text_nosync() for patching arm64/runtime-const: Introduce runtime_const_mask_32() riscv/runtime-const: Replace open-coded placeholder with RUNTIME_MAGIC riscv/runtime-const: Introduce runtime_const_mask_32() s390/runtime-const: Introduce runtime_const_mask_32() Peter Zijlstra (3): x86/runtime-const: Introduce runtime_const_mask_32() asm-generic/runtime-const: Add dummy runtime_const_mask_32() futex: Use runtime constants for __futex_hash() hot path arch/arm64/include/asm/runtime-const.h | 63 ++++++++++++++++---- arch/riscv/include/asm/asm.h | 1 + arch/riscv/include/asm/runtime-const.h | 82 ++++++++++++++++++++------ arch/s390/include/asm/runtime-const.h | 22 ++++++- arch/x86/include/asm/runtime-const.h | 14 +++++ include/asm-generic/runtime-const.h | 1 + include/asm-generic/vmlinux.lds.h | 5 +- kernel/futex/core.c | 44 ++++++++------ 8 files changed, 181 insertions(+), 51 deletions(-) base-commit: 8d0b0ef045143e7ebf2b4c3ad5347bc1e0e45a80 -- 2.34.1