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Wed, 29 Jul 2026 12:03:24 +0200 (CEST) From: Louis-Alexis Eyraud Date: Wed, 29 Jul 2026 12:02:57 +0200 Subject: [PATCH v4 13/24] clk: mediatek: pllfh: Add configurable clock ops to mtk_pllfh_data MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20260729-mt8189-clocks-system-base-v4-13-e356b813a64c@collabora.com> References: <20260729-mt8189-clocks-system-base-v4-0-e356b813a64c@collabora.com> In-Reply-To: <20260729-mt8189-clocks-system-base-v4-0-e356b813a64c@collabora.com> To: Michael Turquette , Stephen Boyd , Brian Masney , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Chun-Jie Chen , Philipp Zabel , Edward-JW Yang , Richard Cochran , Chen-Yu Tsai Cc: kernel@collabora.com, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org, netdev@vger.kernel.org, Louis-Alexis Eyraud X-Mailer: b4 0.14.3 X-Developer-Signature: v=1; a=ed25519-sha256; t=1785319387; l=1909; i=louisalexis.eyraud@collabora.com; s=20250113; h=from:subject:message-id; bh=0Ll+/SLFb8txIVve2YQ50ZAHjghMkBWQteo5ybOHIp4=; b=77MhgRhlTQpzt4t6O+sr+dAbmV+1CQ/GMTzzjqoj7JqqMpI1ei5ey+P0EDUrtIxmOoRSE8QDc ETA1EQlipzWB3IMHCwCY2IaXJHLw6VuQ0ZzWRuNg1fyjmHcz1X8JNUB X-Developer-Key: i=louisalexis.eyraud@collabora.com; a=ed25519; pk=CHFBDB2Kqh4EHc6JIqFn69GhxJJAzc0Zr4e8QxtumuM= X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260729_110327_055351_787CC6DC X-CRM114-Status: GOOD ( 15.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Currently, the mtk_clk_register_pllfh functions always registers the default PLL clock operation set (mtk_pllfh_ops). This does not allow use a custom one, for SoC such as MT8189, that needs different set with support for set/clr enable. Add a new field for the ops to register in mtk_pllfh_data structure and use this new field to either register it when not null or the default ops otherwise. Signed-off-by: Louis-Alexis Eyraud --- drivers/clk/mediatek/clk-pllfh.c | 5 +++-- drivers/clk/mediatek/clk-pllfh.h | 1 + 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/drivers/clk/mediatek/clk-pllfh.c b/drivers/clk/mediatek/clk-pllfh.c index aa95cd9197b3..4878ac6da7da 100644 --- a/drivers/clk/mediatek/clk-pllfh.c +++ b/drivers/clk/mediatek/clk-pllfh.c @@ -153,6 +153,8 @@ static struct clk_hw * mtk_clk_register_pllfh(struct device *dev, const struct mtk_pll_data *pll_data, struct mtk_pllfh_data *pllfh_data, void __iomem *base) { + const struct clk_ops *pllfh_ops = pllfh_data->data.ops ? + pllfh_data->data.ops : &mtk_pllfh_ops; struct clk_hw *hw; struct mtk_fh *fh; int ret; @@ -169,8 +171,7 @@ mtk_clk_register_pllfh(struct device *dev, const struct mtk_pll_data *pll_data, fh->clk_pll.dev = dev; - hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, - &mtk_pllfh_ops); + hw = mtk_clk_register_pll_ops(&fh->clk_pll, pll_data, base, pllfh_ops); if (IS_ERR(hw)) goto out; diff --git a/drivers/clk/mediatek/clk-pllfh.h b/drivers/clk/mediatek/clk-pllfh.h index a4f337acad71..d32bfe194ec4 100644 --- a/drivers/clk/mediatek/clk-pllfh.h +++ b/drivers/clk/mediatek/clk-pllfh.h @@ -34,6 +34,7 @@ struct fh_pll_data { u32 updnlmt_shft; u32 msk_frddsx_dys; u32 msk_frddsx_dts; + const struct clk_ops *ops; }; struct mtk_pllfh_data { -- 2.55.0