From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 7D6E2C54F51 for ; Wed, 29 Jul 2026 14:08:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:Content-Transfer-Encoding: MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:Cc:To:From: Reply-To:Content-Type:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=/TqhIhqUpzpOOzDUBk7hCfNYEZnFrNF+Qqh8CxlP3wY=; b=d8JpGAhNli4/00uy2vPAiKXXpo 3O/2qYrsWMSNTHrkE09WjGfdZ4xU0k+ayTR/u9ypNQgnyF798+Yjl5KjvmVsf196oSq8GVmKQgtO9 jA1hiwZqFMNI72z6cZFk831y3vIyg9v3nYBlKg9tvhjB4WKvzzmnm8aYmCPJm72Y3j7ABrLjJjfm3 TfxxgYC2FVTxl5cWHI+ahbaQJuQnijSD3GWetAcCJclAKgJQvl5pkXuy7hWw9Bf2Drfy7UblVe3AJ cpAIxXc0i4r8FbRRzV580rpdFTXb30loeggD5EjtS5Nfx+jG3Wrvynk+GEIcCS5PePMi0HblWX/AT VXWGDkZg==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wp3Mn-00000007u3M-24Ig; Wed, 29 Jul 2026 12:26:33 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wp3MS-00000007tlf-0xyx for linux-arm-kernel@lists.infradead.org; Wed, 29 Jul 2026 12:26:13 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 435EB1688; Wed, 29 Jul 2026 05:26:07 -0700 (PDT) Received: from a085714.blr.arm.com (a085714.arm.com [10.164.19.28]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id BA9433F66F; Wed, 29 Jul 2026 05:26:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=arm.com; s=foss; t=1785327971; bh=B5C06n+nHY3GH1lL7Fz8Op3mIJsdyU/2KKr0Mpz2km8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dbby0wkQjJDxhPwa2B5hoe4l1aUU3Z2WfTysZOLj6vDiaOlnStimYU/uzN9QvveMo uHc+bX4xreeuGiw6Ykl8RGuIfEjaSwDGyhEq0sR3lsMYh9AKmcJzhD6W1GwxoJvXos yyCP7YIYoXD0ajUAKxB6pW/qG2DGgAx7pDefUVJY= From: Anshuman Khandual To: linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org Cc: Anshuman Khandual , Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , Lorenzo Stoakes , Andrew Morton , David Hildenbrand , Mike Rapoport , Linu Cherian , linux-kernel@vger.kernel.org Subject: [PATCH 15/17] arm64/mm: Add an abstraction level for tlbi_op Date: Wed, 29 Jul 2026 17:54:50 +0530 Message-ID: <20260729122452.3797443-16-anshuman.khandual@arm.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260729122452.3797443-1-anshuman.khandual@arm.com> References: <20260729122452.3797443-1-anshuman.khandual@arm.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260729_052612_348705_3EEF5941 X-CRM114-Status: GOOD ( 10.29 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Linu Cherian With FEAT_D128, a new instruction aka TLBIP is being introduced for the TLB -by-range operations which has an argument size of 128 bit. Add an abstraction level to void (*tlbi_op)(u64 arg) helpers to support the D128 variations when applicable. No functional changes are introduced with this patch. Signed-off-by: Linu Cherian Signed-off-by: Anshuman Khandual --- arch/arm64/include/asm/tlbflush.h | 70 ++++++++++++++++--------------- 1 file changed, 37 insertions(+), 33 deletions(-) diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h index e0e84332f51b..c103380ec87e 100644 --- a/arch/arm64/include/asm/tlbflush.h +++ b/arch/arm64/include/asm/tlbflush.h @@ -130,49 +130,53 @@ static inline void sme_dvmsync_batch(void) #define TLBI_TTL_UNKNOWN INT_MAX -typedef void (*tlbi_op)(u64 arg); +typedef u64 tlbi_arg_t; +#define __tlbi_wrapper(op, arg) __tlbi(op, arg) +#define __tlbi_user_wrapper(op, arg) __tlbi_user(op, arg) -static __always_inline void vae1is(u64 arg) +typedef void (*tlbi_op)(tlbi_arg_t arg); + +static __always_inline void vae1is(tlbi_arg_t arg) { - __tlbi(vae1is, arg); - __tlbi_user(vae1is, arg); + __tlbi_wrapper(vae1is, arg); + __tlbi_user_wrapper(vae1is, arg); } -static __always_inline void vae2is(u64 arg) +static __always_inline void vae2is(tlbi_arg_t arg) { - __tlbi(vae2is, arg); + __tlbi_wrapper(vae2is, arg); } -static __always_inline void vale1(u64 arg) +static __always_inline void vale1(tlbi_arg_t arg) { - __tlbi(vale1, arg); - __tlbi_user(vale1, arg); + __tlbi_wrapper(vale1, arg); + __tlbi_user_wrapper(vale1, arg); } -static __always_inline void vale1is(u64 arg) +static __always_inline void vale1is(tlbi_arg_t arg) { - __tlbi(vale1is, arg); - __tlbi_user(vale1is, arg); + __tlbi_wrapper(vale1is, arg); + __tlbi_user_wrapper(vale1is, arg); } -static __always_inline void vale2is(u64 arg) +static __always_inline void vale2is(tlbi_arg_t arg) { - __tlbi(vale2is, arg); + __tlbi_wrapper(vale2is, arg); } -static __always_inline void vaale1is(u64 arg) +static __always_inline void vaale1is(tlbi_arg_t arg) { - __tlbi(vaale1is, arg); + __tlbi_wrapper(vaale1is, arg); } -static __always_inline void ipas2e1(u64 arg) +static __always_inline void ipas2e1(tlbi_arg_t arg) { - __tlbi(ipas2e1, arg); + __tlbi_wrapper(ipas2e1, arg); } -static __always_inline void ipas2e1is(u64 arg) +static __always_inline void ipas2e1is(tlbi_arg_t arg) { - __tlbi(ipas2e1is, arg); + __tlbi_wrapper(ipas2e1is, arg); } static __always_inline void __tlbi_level_asid(tlbi_op op, u64 addr, u32 level, @@ -443,32 +447,32 @@ static inline void arch_tlbbatch_flush(struct arch_tlbflush_unmap_batch *batch) * operations can only span an even number of pages. We save this for last to * ensure 64KB start alignment is maintained for the LPA2 case. */ -static __always_inline void rvae1is(u64 arg) +static __always_inline void rvae1is(tlbi_arg_t arg) { - __tlbi(rvae1is, arg); - __tlbi_user(rvae1is, arg); + __tlbi_wrapper(rvae1is, arg); + __tlbi_user_wrapper(rvae1is, arg); } -static __always_inline void rvale1(u64 arg) +static __always_inline void rvale1(tlbi_arg_t arg) { - __tlbi(rvale1, arg); - __tlbi_user(rvale1, arg); + __tlbi_wrapper(rvale1, arg); + __tlbi_user_wrapper(rvale1, arg); } -static __always_inline void rvale1is(u64 arg) +static __always_inline void rvale1is(tlbi_arg_t arg) { - __tlbi(rvale1is, arg); - __tlbi_user(rvale1is, arg); + __tlbi_wrapper(rvale1is, arg); + __tlbi_user_wrapper(rvale1is, arg); } -static __always_inline void rvaale1is(u64 arg) +static __always_inline void rvaale1is(tlbi_arg_t arg) { - __tlbi(rvaale1is, arg); + __tlbi_wrapper(rvaale1is, arg); } -static __always_inline void ripas2e1is(u64 arg) +static __always_inline void ripas2e1is(tlbi_arg_t arg) { - __tlbi(ripas2e1is, arg); + __tlbi_wrapper(ripas2e1is, arg); } static __always_inline void __tlbi_range(tlbi_op op, u64 addr, -- 2.43.0