From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id D5272C53219 for ; Wed, 29 Jul 2026 16:56:45 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:List-Subscribe:List-Help :List-Post:List-Archive:List-Unsubscribe:List-Id:In-Reply-To:Content-Type: MIME-Version:Message-ID:Subject:Cc:To:From:Date:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References: List-Owner; bh=Lg59M+bKmHrruSQn5i7qPKBmAeGYaoVMrN0VKxKzTrM=; b=GGXUmuRCIFm5hG 79onK1SHjGxqqryWXWGVnc/8Lqz4prGK4a1ecFRA4EJ/RybLLnHFTX7LCs7sQqp2r+dgya5zMFQH+ yZfL319g4chvgLYZ9dLD3N+071sAQe1dDnN3dRtqVIFe6npDd7cdYF4yZFq/bIVyfdKMisKh3YPJD 0+X0gsTW1ysrm6X6oRjMlwIT5Qm1rmUL1wfY/WQ94FTQVJEg3216Rqkfj2gPTALztv1XJ9HM7PvzX upcx62SxmSfYou8qtenbmwDBJ1+rPUSq9tu3qS0Jh7mLvMON8BGogqXKOueulAPcxEPzPA9cUWX8s vvRB76hPn67rcGvoyYSA==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.99.1 #2 (Red Hat Linux)) id 1wp7aB-00000008dCi-2itQ; Wed, 29 Jul 2026 16:56:39 +0000 Received: from sea.source.kernel.org ([172.234.252.31]) by bombadil.infradead.org with esmtps (Exim 4.99.1 #2 (Red Hat Linux)) id 1wp7aA-00000008dCO-0Sda for linux-arm-kernel@lists.infradead.org; Wed, 29 Jul 2026 16:56:38 +0000 Received: from smtp.kernel.org (quasi.space.kernel.org [100.103.45.18]) by sea.source.kernel.org (Postfix) with ESMTP id 4498A43966; Wed, 29 Jul 2026 16:56:37 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8FD11F000E9; Wed, 29 Jul 2026 16:56:36 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kernel.org; s=k20260515; t=1785344197; bh=Lg59M+bKmHrruSQn5i7qPKBmAeGYaoVMrN0VKxKzTrM=; h=Date:From:To:Cc:Subject:In-Reply-To; b=aL5SNrAfl/7FBVwi4dqKjk5eVIxYFhTTVMqTdhNukNPwCC1CE6NCUyVWOdmSPr1h4 mxgohzFil3hWRkr2d2y6PgHFl4imjHcwRV51eU6FGtKWWzpwn9I9/USNgr4/81s78i +msucwkWhkMJkVXerWWp2YCmxv8DkWwsaJTH4i5DAsmgFCxYVZFCe7QxixwEDpqKEU JId7ehyT/0W6maR37M05/Si74IFdIo0eBP7VugM3SgQD2DJgqDHfkWy1BH25PCH9m1 MwLla81C94JbMiCqP0JR5bb95GJg3C+vEsQDNPWqkgCmWp3ALr1tl/TLgxjNbJx/ix xA8vLXZ6hw/Wg== Date: Wed, 29 Jul 2026 11:56:35 -0500 From: Bjorn Helgaas To: hongxing.zhu@oss.nxp.com Cc: frank.li@nxp.com, l.stach@pengutronix.de, lpieralisi@kernel.org, kwilczynski@kernel.org, mani@kernel.org, robh@kernel.org, bhelgaas@google.com, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org, imx@lists.linux.dev, linux-kernel@vger.kernel.org, Richard Zhu Subject: Re: [PATCH v3] PCI: imx6: Update MPLLB bandwidth to improve i.MX95 Gen3 PCIe stability Message-ID: <20260729165635.GA1450437@bhelgaas> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260714024107.4113926-1-hongxing.zhu@oss.nxp.com> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Jul 14, 2026 at 10:41:07AM +0800, hongxing.zhu@oss.nxp.com wrote: > From: Richard Zhu > > Bandwidth marginality was observed during i.MX95 Gen3 PCIe tests with > the default MPLLB_BANDWIDTH value. This margin degradation worsens > across voltage and temperature (VT) variations and different test > matrices, potentially causing link stability issues. What does "bandwidth marginality" mean? And what does it mean to observe it? I guess it must mean some measurable thing is close to being out of spec? > Testing with MPLLB_BANDWIDTH value of 140 (0x8c) shows significant > improvement in bandwidth margins across all VT conditions and test > scenarios. > > Implement PHY register write helper function and configure: > - MPLLB_BW_OVRD_IN = 140 (0x8c) for improved bandwidth margin > - MPLLB_BW_OVRD_EN to enable the override AFAICT we don't know what MPLLB_BW_OVRD_IN was before, so we don't know whether this increases or decreases the value. And we don't really even know what MPLLB_BW_OVRD_IN specifies. > This ensures robust PCIe Gen3 performance across all operating > conditions. > > Signed-off-by: Richard Zhu > --- > Changes in v3: > Regarding Frank's comments, refine naming consistency and clarity. > > Changes in v2: > Update the register name and bit definitions. > Don't move IMX95_PCIE_PHY_CR_PARA_SEL settings. > --- > drivers/pci/controller/dwc/pci-imx6.c | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/drivers/pci/controller/dwc/pci-imx6.c b/drivers/pci/controller/dwc/pci-imx6.c > index 53f3da6ab30d5..fadf14de10f7c 100644 > --- a/drivers/pci/controller/dwc/pci-imx6.c > +++ b/drivers/pci/controller/dwc/pci-imx6.c > @@ -80,6 +80,17 @@ > #define IMX95_SID_MASK GENMASK(5, 0) > #define IMX95_MAX_LUT 32 > > +#define IMX95_PCIE_PHY_REG_ADDR 0x3008 > +#define IMX95_PCIE_PHY_REG_EN BIT(31) > +#define IMX95_PCIE_PHY_REG_ADDR_MASK GENMASK(15, 0) > +#define IMX95_PCIE_PHY_REG_DATA 0x300c > +#define IMX95_PCIE_PHY_MPLLB_OVRD_IN 0x2004 > +/* BIT(10): Override enable for mpllb_bandwidth[15:0] */ > +#define IMX95_PCIE_PHY_MPLLB_OVRD_BW_EN 0x400 > +/* Register offset: Override value for mpllb_bandwidth[15:0] */ > +#define IMX95_PCIE_PHY_MPLLB_BW_IN 0x2005 > +#define IMX95_PCIE_PHY_MPLLB_BW_VAL 0x8c > + > #define IMX95_PCIE_RST_CTRL 0x3010 > #define IMX95_PCIE_COLD_RST BIT(0) > > @@ -269,6 +280,16 @@ static int imx95_pcie_select_ref_clk_src(struct imx_pcie *imx_pcie) > return 0; > } > > +static void imx95_pcie_phy_write(struct imx_pcie *imx_pcie, int addr, u16 data) > +{ > + udelay(200); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_ADDR, > + IMX95_PCIE_PHY_REG_EN, IMX95_PCIE_PHY_REG_EN); > + regmap_update_bits(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_ADDR, > + IMX95_PCIE_PHY_REG_ADDR_MASK, addr); > + regmap_write(imx_pcie->iomuxc_gpr, IMX95_PCIE_PHY_REG_DATA, data); > +} > + > static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) > { > /* > @@ -289,6 +310,11 @@ static int imx95_pcie_init_phy(struct imx_pcie *imx_pcie) > IMX95_PCIE_PHY_CR_PARA_SEL, > IMX95_PCIE_PHY_CR_PARA_SEL); > > + imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_BW_IN, > + IMX95_PCIE_PHY_MPLLB_BW_VAL); > + imx95_pcie_phy_write(imx_pcie, IMX95_PCIE_PHY_MPLLB_OVRD_IN, > + IMX95_PCIE_PHY_MPLLB_OVRD_BW_EN); > + > return 0; > } > > -- > 2.34.1 >