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[86.96.6.50]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd456a5a4sm1751576f8f.20.2026.07.31.00.36.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 31 Jul 2026 00:36:05 -0700 (PDT) From: Abid Ali To: kuba@kernel.org Cc: alexandre.torgue@foss.st.com, andrew+netdev@lunn.ch, davem@davemloft.net, dev.taqnialabs@gmail.com, edumazet@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, maxime.chevallier@bootlin.com, mcoquelin.stm32@gmail.com, netdev@vger.kernel.org, pabeni@redhat.com Subject: Re: [PATCH v2] net: stmmac: enable MAC rx/tx after DMA start Date: Fri, 31 Jul 2026 07:35:48 +0000 Message-ID: <20260731073548.1145-1-dev.taqnialabs@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260730160715.5ba5e272@kernel.org> References: <20260730160715.5ba5e272@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260731_003608_578718_B0AC3E15 X-CRM114-Status: GOOD ( 15.84 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, 30 Jul 2026 16:07:15 -0700 Jakub Kicinski wrote: > Looking at the patch - isn't it a bit awkward to handle Rx and Tx > together? We want to keep Rx blocked to prevent incoming frames, > but Tx should be allowed so that Tx can egress? netif_tx_start_all_queues() runs after stmmac_mac_set() in both __stmmac_open() and stmmac_xdp_open(), so no frame can be queued in the window between DMA start and MAC enable. So I expect this reorder to be fine and see no issue of coupling them together. > Grepping around I'm not seeing any flushing of Tx. Aren't there > issues with this driver if we stop the interface while it was > paused by link partner? I haven't run into these issues myself, but as Qingfang noted in this thread the proper release sequence per the programming guide needs more steps: stop TX DMA -> wait TPS (TX DMA stop confirmation) -> wait TX drain -> disable MAC RX/TX -> drain RX FIFO -> stop RX DMA -> wait RPS This is a pre-existing gap in the driver, currently it just clears the SR/ST bits for each channel and returns. Implementing the proper sequence would need readl_poll_timeout on TPS/RPS status bits per channel (up to 16 TX + 16 RX in my case), plus handling timeouts if the status never updates in teardown. The startup reorder is tested and verified to fix the RX hang I have seen. Would it make sense to take this on its own (only the startup reorder, with the teardown changes removed from v2) and address the teardown at a later point as I see multiple open points on what would be the right implementation to have there. Thanks, Abid