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Fri, 31 Jul 2026 14:50:40 +0000 (GMT) Received: from osiris (unknown [9.111.39.121]) by smtpav03.fra02v.mail.ibm.com (Postfix) with ESMTPS; Fri, 31 Jul 2026 14:50:40 +0000 (GMT) Date: Fri, 31 Jul 2026 16:50:39 +0200 From: Steffen Eiden To: Marc Zyngier Cc: kvm@vger.kernel.org, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-s390@vger.kernel.org, Alexander Gordeev , Andreas Grapentin , Arnd Bergmann , Catalin Marinas , Christian Borntraeger , Claudio Imbrenda , David Hildenbrand , Friedrich Welter , Fuad Tabba , Gautam Gala , Hariharan Mari , Heiko Carstens , Hendrik Brueckner , Ilya Leoshkevich , Janosch Frank , Joey Gouly , Nico Boehr , Nina Schoetterl-Glausch , Oliver Upton , Paolo Bonzini , Suzuki K Poulose , Sven Schnelle , Ulrich Weigand , Vasily Gorbik , Will Deacon , Zenghui Yu Subject: Re: [PATCH v5 06/31] arm64/sysreg: Convert SPSR_ELx to automatic register generation Message-ID: <20260731145039.1016137-A-seiden@linux.ibm.com> References: <20260731130902.654679-1-seiden@linux.ibm.com> <20260731130902.654679-7-seiden@linux.ibm.com> <86bjbnckge.wl-maz@kernel.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <86bjbnckge.wl-maz@kernel.org> X-TM-AS-GCONF: 00 X-Proofpoint-Reinject: loops=2 maxloops=12 X-Proofpoint-GUID: vfPmpKOMLhAfiWmTk8SICmYmFgUzRJeL X-Proofpoint-ORIG-GUID: 7dSkOPs6jV62dQ5msdvicZhLLQ6hkmSC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwNzMxMDExMyBTYWx0ZWRfX/zzVQqF7gPiR 2WETnBc7I2gDjPTDVBD8zUbin5HavD3mjFLxs0+F/VZaZAnEhb92if+tXXfD2XY8jU87s/Fgl9j Y0fSvvsrgxg3vPlEb1Tr00UOFKzBgP4bqLEu5lXOrU4k2V17fC3vsQuaR17Shj/a18nEStMQx9o q6kGldh7Wdkjh1mzj28F2mxjtF5KDHqElF1e+jGE6XZJTA+UyiwKJsem9A9jZGyRLAuUhxphpEo l55mm3oF41YWJuL1tPSUkutbQhRiAiVdcWp+z0eYR5Cwe8ZGf7D+Cmat8jTNQgaf8s0db7Fm2yN dEJJkemCouWZ3rwsMQG/WhknteyewD2AYuXHlCacLcS9sXY23NZb0KlZNu2BrDVPqeC8QMNv2XK o6PhTQJTWQvAp2jn8Gc25jAFXTNwQ0lppTMHxOlww8dfh3Sz7GBjBpuZ1xbIHmVe4m+nEOh9TvF OFogZb+lRfOkUdgNzyg== X-Authority-Analysis: v=2.4 cv=SKFykuvH c=1 sm=1 tr=0 ts=6a6cb64a cx=c_pps a=AfN7/Ok6k8XGzOShvHwTGQ==:117 a=AfN7/Ok6k8XGzOShvHwTGQ==:17 a=kj9zAlcOel0A:10 a=RAioF0-LDSMA:10 a=VkNPw1HP01LnGYTKEx00:22 a=RnoormkPH1_aCDwRdu11:22 a=iQ6ETzBq9ecOQQE5vZCe:22 a=VnNF1IyMAAAA:8 a=20fFOLQ9k4DZ6xVQLREA:9 a=CjuIK1q_8ugA:10 X-Proofpoint-Spam-Info: AW1haW4tMjYwNzMxMDExMyBTYWx0ZWRfXyIt6Pe3/YoLx OyclkoRVaTDoTkevi9+MoD2L5phRQYcisNLA8tDkqPtI0kO01F8/3MQ8EXyUDvBSCduhScdnuFF cmQQuITycm1WzIIghIVadacARNktt0M= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1143,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-07-31_04,2026-07-30_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 malwarescore=0 clxscore=1015 adultscore=0 lowpriorityscore=0 bulkscore=0 impostorscore=0 phishscore=0 spamscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2607310113 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260731_075102_601345_86136387 X-CRM114-Status: GOOD ( 26.96 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Jul 31, 2026 at 03:17:21PM +0100, Marc Zyngier wrote: > On Fri, 31 Jul 2026 14:08:34 +0100, > Steffen Eiden wrote: > > > > Convert SPSR_EL{1, 2, 12} to automatic register generation as per > > DDIO616 2026-06. No functional change. > > > > Signed-off-by: Steffen Eiden > > --- > > arch/arm64/include/asm/sysreg.h | 3 -- > > arch/arm64/tools/sysreg | 72 +++++++++++++++++++++++++++++++++ > > 2 files changed, 72 insertions(+), 3 deletions(-) > > > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > > index 4bfdac9401bd..1aa601c95188 100644 > > --- a/arch/arm64/include/asm/sysreg.h > > +++ b/arch/arm64/include/asm/sysreg.h > > @@ -295,7 +295,6 @@ > > #define SYS_APGAKEYLO_EL1 sys_reg(3, 0, 2, 3, 0) > > #define SYS_APGAKEYHI_EL1 sys_reg(3, 0, 2, 3, 1) > > > > -#define SYS_SPSR_EL1 sys_reg(3, 0, 4, 0, 0) > > #define SYS_ELR_EL1 sys_reg(3, 0, 4, 0, 1) > > > > #define SYS_ICC_PMR_EL1 sys_reg(3, 0, 4, 6, 0) > > @@ -518,7 +517,6 @@ > > #define SYS_VTTBR_EL2 sys_reg(3, 4, 2, 1, 0) > > > > #define SYS_HAFGRTR_EL2 sys_reg(3, 4, 3, 1, 6) > > -#define SYS_SPSR_EL2 sys_reg(3, 4, 4, 0, 0) > > #define SYS_ELR_EL2 sys_reg(3, 4, 4, 0, 1) > > #define SYS_SP_EL1 sys_reg(3, 4, 4, 1, 0) > > #define SYS_SPSR_irq sys_reg(3, 4, 4, 3, 0) > > @@ -604,7 +602,6 @@ > > #define SYS_BRBCR_EL12 sys_reg(2, 5, 9, 0, 0) > > #define SYS_TTBR0_EL12 sys_reg(3, 5, 2, 0, 0) > > #define SYS_TTBR1_EL12 sys_reg(3, 5, 2, 0, 1) > > -#define SYS_SPSR_EL12 sys_reg(3, 5, 4, 0, 0) > > #define SYS_ELR_EL12 sys_reg(3, 5, 4, 0, 1) > > #define SYS_AFSR0_EL12 sys_reg(3, 5, 5, 1, 0) > > #define SYS_AFSR1_EL12 sys_reg(3, 5, 5, 1, 1) > > diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg > > index 7cb61aca3797..2a4b94e8c62f 100644 > > --- a/arch/arm64/tools/sysreg > > +++ b/arch/arm64/tools/sysreg > > @@ -401,6 +401,78 @@ Res0 3:1 > > Field 0 SO > > EndSysreg > > > > +Sysreg SPSR_EL1 3 0 4 0 0 > > +Res0 63:37 > > +Field 36 UNIJ > > +Res0 35:34 > > +Field 33 PPEND > > +Res0 32 > > +Field 31 N > > +Field 30 Z > > +Field 29 C > > +Field 28 V > > +Field 27 Q > > +Field 26:25 IT01 > > +Field 24 DIT > > +Field 23 SSBS > > +Field 22 PAN > > +Field 21 SS > > +Field 20 IL > > +Field 19:16 GE > > +Field 15:10 IT27 > > I'm sorry, but this is complete nonsense. It looks like you have > lifted the AArch32 version of the definition, and not the AArch64 view > (which really is what matters here). dang. Yes, I successfully confused myself here. You are absoultely right I accidentlially picked the AArch32 variant. I will fix this with the next round. > > > +Field 9 E > > +Field 8 A > > +Field 7 I > > +Field 6 F > > +Field 5 T > > +Field 4 M4 > > +Enum 3:0 M > > I don't think you should split the M field as such. The AArch32 > encoding uses bit 4, and should be described. Ok. I copied the defenitions directly from the arm architecure and it differntiated between the frist 3 bits of M and the 4th. (for 32 and 64 bit). I will merge it. > > > + 0b0000 EL0 > > + 0b0100 EL1t > > + 0b0101 EL1h > > + 0b1000 EL1tnv > > + 0b1001 EL1hnv > > Please do *not* invent names. These are EL2t/EL2h, and cannot be > anything else. will change. thanks. Steffen > > M. > > -- > Without deviation from the norm, progress is not possible.