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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2d04b120f2fsm33679845ad.64.2026.08.03.00.49.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 00:49:43 -0700 (PDT) From: Chi-Wen Weng To: broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cwweng@nuvoton.com, cwweng.linux@gmail.com Subject: [PATCH v3 2/2] spi: ma35d1-qspi: Enable GPIO chip selects Date: Mon, 3 Aug 2026 15:49:13 +0800 Message-Id: <20260803074913.1656675-3-cwweng.linux@gmail.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20260803074913.1656675-1-cwweng.linux@gmail.com> References: <5769eae0-1b40-419f-8311-0d919bf619fa@sirena.org.uk> <20260803074913.1656675-1-cwweng.linux@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260803_004945_457665_93C1E6EB X-CRM114-Status: GOOD ( 17.34 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Chi-Wen Weng The generic SPI controller binding allows GPIO-based chip selects, but the MA35D1 QSPI driver does not currently enable the SPI core's GPIO descriptor handling. Enable GPIO chip-select support and distinguish the total number of chip selects from the controller's two native chip selects. Allow num-cs to include additional GPIO chip selects and set max_native_cs to the native hardware limit. Add a setup callback that rejects chip-select indices beyond the native limit when no GPIO descriptor is present. Also reject active-high polarity only for native chip selects, while allowing GPIO chip-select polarity to be handled by the GPIO subsystem. Signed-off-by: Chi-Wen Weng --- drivers/spi/spi-ma35d1-qspi.c | 32 ++++++++++++++++++++++++++++---- 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/drivers/spi/spi-ma35d1-qspi.c b/drivers/spi/spi-ma35d1-qspi.c index 541d5d72484c..f893a4160528 100644 --- a/drivers/spi/spi-ma35d1-qspi.c +++ b/drivers/spi/spi-ma35d1-qspi.c @@ -61,7 +61,7 @@ #define NUVOTON_QSPI_STATUS_RXEMPTY_MASK BIT(8) /* Receive FIFO Empty */ #define NUVOTON_QSPI_STATUS_BUSY_MASK BIT(0) /* Busy Status */ -#define NUVOTON_QSPI_MAX_NUM_CS 2 +#define NUVOTON_QSPI_MAX_NATIVE_CS 2 #define NUVOTON_QSPI_DEFAULT_NUM_CS 2 #define NUVOTON_QSPI_DEFAULT_BPW 8 /* Bound PIO operations to avoid long atomic polling loops. */ @@ -430,13 +430,34 @@ static void nuvoton_qspi_set_cs_level(struct nuvoton_qspi *qspi, spin_unlock_irqrestore(&qspi->ssctl_lock, flags); } +static int nuvoton_qspi_setup(struct spi_device *spi) +{ + unsigned int cs = spi_get_chipselect(spi, 0); + + if (spi_get_csgpiod(spi, 0)) + return 0; + + if (cs >= NUVOTON_QSPI_MAX_NATIVE_CS) { + dev_err(&spi->dev, "invalid native chip select %u\n", cs); + return -EINVAL; + } + + if (spi->mode & SPI_CS_HIGH) { + dev_err(&spi->dev, + "active-high native chip select is not supported\n"); + return -EINVAL; + } + + return 0; +} + static void nuvoton_qspi_set_cs(struct spi_device *spi, bool level) { struct nuvoton_qspi *qspi = spi_controller_get_devdata(spi->controller); /* - * The SPI core passes the physical CS level to ->set_cs(). This - * initial driver only supports active-low native chip selects. + * The SPI core passes the physical CS level to ->set_cs(). Native + * chip selects are active low. */ nuvoton_qspi_set_cs_level(qspi, spi_get_chipselect(spi, 0), !level); } @@ -608,15 +629,18 @@ static int nuvoton_qspi_probe(struct platform_device *pdev) if (ret && ret != -EINVAL) return dev_err_probe(dev, ret, "failed to read num-cs\n"); - if (!num_cs || num_cs > NUVOTON_QSPI_MAX_NUM_CS) + if (!num_cs) return dev_err_probe(dev, -EINVAL, "invalid num-cs %u\n", num_cs); ctlr->num_chipselect = num_cs; + ctlr->max_native_cs = NUVOTON_QSPI_MAX_NATIVE_CS; + ctlr->use_gpio_descriptors = true; ctlr->max_transfer_size = nuvoton_qspi_max_transfer_size; ctlr->max_message_size = nuvoton_qspi_max_message_size; ctlr->mem_ops = &nuvoton_qspi_mem_ops; ctlr->mem_caps = &nuvoton_qspi_mem_caps; + ctlr->setup = nuvoton_qspi_setup; ctlr->set_cs = nuvoton_qspi_set_cs; ctlr->transfer_one = nuvoton_qspi_transfer_one; ctlr->bits_per_word_mask = SPI_BPW_MASK(8); -- 2.25.1