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Mon, 03 Aug 2026 15:46:16 -0700 (PDT) X-Received: by 2002:a05:6a21:9f10:b0:3b4:931c:3c7c with SMTP id adf61e73a8af0-3c92a7bb452mr11971714637.44.1785797176358; Mon, 03 Aug 2026 15:46:16 -0700 (PDT) Received: from localhost ([50.35.46.84]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-13fab2530c0sm34545273c88.8.2026.08.03.15.46.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 15:46:16 -0700 (PDT) Date: Mon, 3 Aug 2026 15:46:11 -0700 From: Jonathan Cameron To: Andre Przywara Cc: Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Catalin Marinas , Will Deacon , "Rafael J . Wysocki" , Len Brown , James Morse , Ben Horgan , Reinette Chatre , Fenghua Yu , Jonathan Cameron , Srivathsa L Rao , Ganapatrao Kulkarni , Trilok Soni , Srinivas Ramana , Niyas Sait , Lee Trager , Ritwick Sharma , linux-acpi@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v7 10/11] arm_mpam: change MPAM-Fb error IRQ to use a threaded IRQ handler Message-ID: <20260803154611.00007d6d@oss.qualcomm.com> In-Reply-To: <20260731170324.2927758-11-andre.przywara@arm.com> References: <20260731170324.2927758-1-andre.przywara@arm.com> <20260731170324.2927758-11-andre.przywara@arm.com> Organization: Qualcomm X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit X-Authority-Analysis: v=2.4 cv=X9Ri7mTe c=1 sm=1 tr=0 ts=6a711a39 cx=c_pps a=Qgeoaf8Lrialg5Z894R3/Q==:117 a=qC1CW/w66vtJz1P9yTJxNA==:17 a=kj9zAlcOel0A:10 a=Sv0fKeRqtYgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=7CQSdrXTAAAA:8 a=EUspDBNiAAAA:8 a=ePHNPm31KbGbtx5XAOQA:9 a=CjuIK1q_8ugA:10 a=x9snwWr2DeNwDh03kgHS:22 a=a-qgeE7W1pNrGK8U0ZQC:22 X-Proofpoint-ORIG-GUID: v-JXPkD4AmWV9dxMi_DTIiwTZOYGL1GM X-Proofpoint-GUID: v-JXPkD4AmWV9dxMi_DTIiwTZOYGL1GM X-Proofpoint-Spam-Info: AW1haW4tMjYwODAzMDIwMCBTYWx0ZWRfX2amCnkkDNycb Yd6E4RiCnQUNhCsnYWi5Aub4e9BGCnpRNghH26yfrVuUOx/RWtXINENTcG1wZBU6vmViSH+JKBg EAe19JxnN7PifpWjmJOvOric70ewTyM= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYwODAzMDIwMCBTYWx0ZWRfX4QcUNkMbPCns Xp3UVs3KSH/97dg9414bxYivt+yOGaUklHFO8+9zhy+jo0dBUM6PTpY0govZ0FtN0fB+pec8mYA U0YcqGqUC4FijNF7h/97q2Fa097JqnH2K/ht0iexKWtbNc2tCBKj4TzaiYghcdz8gkGY83FfljW 4UP2dVsdDij0CB1pp49YGYifAWsDsDpbUm4tn6dpfGFrfzBen+RMsoLnR0HaHWX+if04Zh2aXmm BWL2znX8QS6xsmyYvpP39kB7xg5PvcrcNPwBZYUhNbz6MmhAUHm6SMw3ZfXxh35vK5lxvVowdRh z1P/h7bquVcQTrPHYIzgdySX+YF64NOrTG0q1cI/gVh1DVypEoSLliAaUqHrdwJpyQYQ+3R8MU6 3VwTnBxmtUi7ZQlrVZfUS0A1b7m9YJYIIvJcqXQAoejrCMXr1MPRX0QvxpgB9vymdn/U8wWXJ1P 2CWQpU4zM0qywxv54WA== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-08-03_05,2026-08-03_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 impostorscore=0 bulkscore=0 malwarescore=0 priorityscore=1501 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2606150000 definitions=main-2608030200 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260803_154619_036026_B507A454 X-CRM114-Status: GOOD ( 37.14 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, 31 Jul 2026 19:03:23 +0200 Andre Przywara wrote: > When an MPAM MSC gets into an error condition, it can trigger an error > IRQ. We cannot really do much about those errors, but we at least query > and log the error, then disable MPAM functionality. > > This error report relies on reading the MSC's error status register > (ESR) in the current hard-IRQ handler, which is not possible for MPAM-Fb > based MSC accesses, since they involve mailbox routines that might sleep. > The same is true for clearing the interrupt at the source, which requires > an MSC access as well. > > When an MSC is using MPAM-Fb, change the error IRQ to use a threaded IRQ > handler, with an empty hard IRQ routine, and doing all the MSC accesses > (to access the status and disable the IRQ line) in the threaded part. > Also forbid per-CPU interrupts (PPIs) for MPAM-Fb, as we cannot use a > threaded IRQ here. > > The change in the actual IRQ handler is minimal, we just check for the > first MSC access error and bail out early. MMIO based MSCs keep using a > hard-IRQ handler, since they must be at least non-migrate-able when doing > MSC accesses, for the CPU affinity check to work. > > Signed-off-by: Andre Przywara A small thing inline about a refactor that I can't spot a reason for. May it's one of those cases where the code evolved into something that would benefit from another look. Either way I'm fine with this Reviewed-by: Jonathan Cameron > --- > drivers/resctrl/mpam_devices.c | 52 +++++++++++++++++++++++++--------- > 1 file changed, 39 insertions(+), 13 deletions(-) > > diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_devices.c > index ea08c12f717a..b238feb559d4 100644 > --- a/drivers/resctrl/mpam_devices.c > +++ b/drivers/resctrl/mpam_devices.c > @@ -2741,19 +2755,19 @@ static irqreturn_t __mpam_irq_handler(int irq, struct mpam_msc *msc) > msc->id, mpam_errcode_names[errcode], partid, pmg, > ris); > > - /* Disable this interrupt. */ > +out_disable: > + /* Disable this interrupt. Ignore errors, we need to proceed anyway. */ > mpam_disable_msc_ecr(msc); > > - /* Are we racing with the thread disabling MPAM? */ > - if (!mpam_is_enabled()) > - return IRQ_HANDLED; > - > /* > - * Schedule the teardown work. Don't use a threaded IRQ as we can't > - * unregister the interrupt from the threaded part of the handler. > + * Schedule the teardown work. We have to defer it as we can't > + * unregister the interrupt from the threaded part of a handler. > + * Check whether we are racing with the thread disabling MPAM. > */ > - mpam_disable_reason = "hardware error interrupt"; > - schedule_work(&mpam_broken_work); > + if (mpam_is_enabled()) { > + mpam_disable_reason = "hardware error interrupt"; > + schedule_work(&mpam_broken_work); > + } Why the logic flip here? (!mpam_is_enabled() and early return vs if (mpam_is_enabled()) It seems to be doing exactly the same. Is it to couple the comment more tightly with the code? I don't mind it done this way but it is a reasonable amount of churn for no strong benefit that I can immediately spot. > > return IRQ_HANDLED; > }