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Mon, 03 Aug 2026 11:08:05 -0700 (PDT) Received: from localhost.localdomain ([2a0d:3344:2841:7708:a101:2b8a:f76:a00f]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-47fd42d91b3sm37950955f8f.14.2026.08.03.11.08.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Aug 2026 11:08:05 -0700 (PDT) From: =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= To: mturquette@baylibre.com, sboyd@kernel.org, wens@kernel.org, jernej.skrabec@gmail.com, samuel@sholland.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org Cc: andre.przywara@arm.com, bmasney@redhat.com, linux-clk@vger.kernel.org, linux-sunxi@lists.linux.dev, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, =?UTF-8?q?Juan=20Manuel=20L=C3=B3pez=20Carrillo?= Subject: [PATCH v2 3/3] arm64: dts: allwinner: a523: add GPU OPP table Date: Mon, 3 Aug 2026 20:07:55 +0200 Message-ID: <20260803180755.288793-4-juanmanuellopezcarrillo@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260803180755.288793-1-juanmanuellopezcarrillo@gmail.com> References: <20260803180755.288793-1-juanmanuellopezcarrillo@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260803_110807_673762_F8E2B1BD X-CRM114-Status: GOOD ( 13.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Add the Mali-G57 operating points from the vendor BSP universal table (150/200/300/400/600 MHz) so panfrost devfreq can scale the GPU instead of running at the boot clock. The table describes the SoC rather than any particular board, so it lives in the .dtsi and is referenced from the GPU node there; every A523/T527 board in tree already provides mali-supply. The BSP universal table specifies 900 mV for all of these operating points, so that is the target and minimum voltage. The maximum is set to 920 mV to also cover boards whose GPU rail is a fixed 920 mV supply (the Orange Pi 4A drives it from AXP717 DCDC2, fixed at 920 mV), where the voltage transitions are then no-ops. The higher speed-bin points of the BSP (648-792 MHz) are not included: they are gated by a SID efuse bin and need pll-gpu as a live parent. Depends on the sun55i-a523 GPU clock divider fix: the OPP rates are only produced correctly with the cycle-masking divider model. Validated on hardware with the Mali cycle counter: 149/199/300/399/597 MHz measured under load, thermal-emulation throttling included. Signed-off-by: Juan Manuel López Carrillo --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 30 +++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi index 85ef492ffeae..a3164b5dd609 100644 --- a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -85,6 +85,35 @@ osc24M: osc24M-clk { clock-output-names = "osc24M"; }; + gpu_opp_table: opp-table-gpu { + compatible = "operating-points-v2"; + + opp-150000000 { + opp-hz = /bits/ 64 <150000000>; + opp-microvolt = <900000 900000 920000>; + }; + + opp-200000000 { + opp-hz = /bits/ 64 <200000000>; + opp-microvolt = <900000 900000 920000>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + opp-microvolt = <900000 900000 920000>; + }; + + opp-400000000 { + opp-hz = /bits/ 64 <400000000>; + opp-microvolt = <900000 900000 920000>; + }; + + opp-600000000 { + opp-hz = /bits/ 64 <600000000>; + opp-microvolt = <900000 900000 920000>; + }; + }; + pmu { compatible = "arm,cortex-a55-pmu"; interrupts = ; @@ -121,6 +150,7 @@ gpu: gpu@1800000 { interrupt-names = "job", "mmu", "gpu"; clocks = <&ccu CLK_GPU>, <&ccu CLK_BUS_GPU>; clock-names = "core", "bus"; + operating-points-v2 = <&gpu_opp_table>; power-domains = <&pck600 PD_GPU>; resets = <&ccu RST_BUS_GPU>; status = "disabled"; -- 2.47.3