From: Yu-Chun Lin <eleanor.lin@realtek.com>
To: <mturquette@baylibre.com>, <sboyd@kernel.org>, <robh@kernel.org>,
<krzk+dt@kernel.org>, <conor+dt@kernel.org>,
<p.zabel@pengutronix.de>, <cylee12@realtek.com>,
<jyanchou@realtek.com>, <bmasney@redhat.com>
Cc: <afaerber@suse.com>, <devicetree@vger.kernel.org>,
<linux-clk@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-realtek-soc@lists.infradead.org>, <james.tai@realtek.com>,
<cy.huang@realtek.com>, <stanley_chang@realtek.com>,
<eleanor.lin@realtek.com>
Subject: [PATCH v12 04/11] clk: realtek: Introduce common probe() and remove()
Date: Wed, 5 Aug 2026 00:38:00 +0800 [thread overview]
Message-ID: <20260804163807.1285869-5-eleanor.lin@realtek.com> (raw)
In-Reply-To: <20260804163807.1285869-1-eleanor.lin@realtek.com>
From: Cheng-Yu Lee <cylee12@realtek.com>
Add rtk_clk_probe() to set up the shared regmap, register clock hardware,
and add the clock provider.
Add rtk_clk_remove() to clear the regmap pointers in the clock descriptors
during driver unbind to prevent dangling pointers.
Additionally, if the "#reset-cells" property is present in the device tree,
it creates and registers an auxiliary device using the provided aux_name.
This allows the dedicated reset driver to bind to this device, enabling
both clock and reset drivers to share the same regmap.
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Cheng-Yu Lee <cylee12@realtek.com>
Co-developed-by: Yu-Chun Lin <eleanor.lin@realtek.com>
Signed-off-by: Yu-Chun Lin <eleanor.lin@realtek.com>
---
Changes in v12:
- Add rtk_clk_remove().
- Rename symbol namespace from REALTEK_CLK to CLK_REALTEK.
- Add Reviewed-by tag from Brian.
---
MAINTAINERS | 1 +
drivers/clk/Kconfig | 1 +
drivers/clk/Makefile | 1 +
drivers/clk/realtek/Kconfig | 30 ++++++++++
drivers/clk/realtek/Makefile | 4 ++
drivers/clk/realtek/clk-rtk-common.c | 83 ++++++++++++++++++++++++++++
drivers/clk/realtek/clk-rtk-common.h | 38 +++++++++++++
7 files changed, 158 insertions(+)
create mode 100644 drivers/clk/realtek/Kconfig
create mode 100644 drivers/clk/realtek/Makefile
create mode 100644 drivers/clk/realtek/clk-rtk-common.c
create mode 100644 drivers/clk/realtek/clk-rtk-common.h
diff --git a/MAINTAINERS b/MAINTAINERS
index a752551f32f9..e55eb1c06119 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -22746,6 +22746,7 @@ M: Cheng-Yu Lee <cylee12@realtek.com>
M: Yu-Chun Lin <eleanor.lin@realtek.com>
S: Supported
F: Documentation/devicetree/bindings/clock/realtek*
+F: drivers/clk/realtek/*
F: drivers/reset/realtek/*
F: include/dt-bindings/clock/realtek*
F: include/dt-bindings/reset/realtek*
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 1717ce75a907..97ad817457db 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -525,6 +525,7 @@ source "drivers/clk/nuvoton/Kconfig"
source "drivers/clk/pistachio/Kconfig"
source "drivers/clk/qcom/Kconfig"
source "drivers/clk/ralink/Kconfig"
+source "drivers/clk/realtek/Kconfig"
source "drivers/clk/renesas/Kconfig"
source "drivers/clk/rockchip/Kconfig"
source "drivers/clk/samsung/Kconfig"
diff --git a/drivers/clk/Makefile b/drivers/clk/Makefile
index cc108a75a900..b1aa373e9f84 100644
--- a/drivers/clk/Makefile
+++ b/drivers/clk/Makefile
@@ -141,6 +141,7 @@ obj-$(CONFIG_COMMON_CLK_PISTACHIO) += pistachio/
obj-$(CONFIG_COMMON_CLK_PXA) += pxa/
obj-$(CONFIG_COMMON_CLK_QCOM) += qcom/
obj-y += ralink/
+obj-$(CONFIG_COMMON_CLK_REALTEK) += realtek/
obj-y += renesas/
obj-$(CONFIG_COMMON_CLK_ROCKCHIP) += rockchip/
obj-$(CONFIG_COMMON_CLK_SAMSUNG) += samsung/
diff --git a/drivers/clk/realtek/Kconfig b/drivers/clk/realtek/Kconfig
new file mode 100644
index 000000000000..ed97531e321d
--- /dev/null
+++ b/drivers/clk/realtek/Kconfig
@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-only
+config COMMON_CLK_REALTEK
+ tristate "Clock driver for Realtek SoCs"
+ depends on ARCH_REALTEK || COMPILE_TEST
+ default ARCH_REALTEK
+ help
+ Enable the common clock framework infrastructure for Realtek
+ system-on-chip platforms.
+
+ This provides the base support required by individual Realtek
+ clock controller drivers to expose clocks to peripheral devices.
+
+ If you have a Realtek-based platform, say Y.
+
+if COMMON_CLK_REALTEK
+
+config RTK_CLK_COMMON
+ tristate "Realtek Clock Common"
+ depends on RESET_CONTROLLER
+ select AUXILIARY_BUS
+ select MFD_SYSCON
+ select RESET_RTK_COMMON
+ help
+ Common helper code shared by Realtek clock controller drivers.
+
+ This provides utility functions and data structures used by
+ multiple Realtek clock implementations, and include integration
+ with reset controllers where required.
+
+endif
diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile
new file mode 100644
index 000000000000..13000ed4ba11
--- /dev/null
+++ b/drivers/clk/realtek/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0-only
+obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o
+
+clk-rtk-y += clk-rtk-common.o
diff --git a/drivers/clk/realtek/clk-rtk-common.c b/drivers/clk/realtek/clk-rtk-common.c
new file mode 100644
index 000000000000..e8422ecbad79
--- /dev/null
+++ b/drivers/clk/realtek/clk-rtk-common.c
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2019-2026 Realtek Semiconductor Corporation
+ * Author: Cheng-Yu Lee <cylee12@realtek.com>
+ */
+
+#include <linux/auxiliary_bus.h>
+#include <linux/device.h>
+#include <linux/export.h>
+#include <linux/mfd/syscon.h>
+#include <linux/module.h>
+#include <linux/platform_device.h>
+#include "clk-rtk-common.h"
+
+static int rtk_reset_controller_register(struct device *dev, const char *aux_name,
+ struct regmap *map)
+{
+ struct auxiliary_device *adev;
+
+ if (!of_property_present(dev->of_node, "#reset-cells"))
+ return 0;
+
+ if (!aux_name) {
+ dev_err(dev, "DTS requires reset controller, but aux_name is missing\n");
+ return -EINVAL;
+ }
+
+ adev = devm_auxiliary_device_create(dev, aux_name, (void *)map);
+ if (!adev)
+ return -ENOMEM;
+
+ return 0;
+}
+
+int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc)
+{
+ struct device *dev = &pdev->dev;
+ struct regmap *regmap;
+ struct clk_hw *hw;
+ int i, ret;
+
+ regmap = device_node_to_regmap(dev->of_node);
+ if (IS_ERR(regmap))
+ return dev_err_probe(dev, PTR_ERR(regmap), "failed to get regmap\n");
+
+ for (i = 0; i < desc->num_clks; i++)
+ desc->clks[i]->regmap = regmap;
+
+ for (i = 0; i < desc->clk_data->num; i++) {
+ hw = desc->clk_data->hws[i];
+ if (!hw)
+ continue;
+
+ ret = devm_clk_hw_register(dev, hw);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to register hw of clk%d\n", i);
+ }
+
+ ret = devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get,
+ desc->clk_data);
+ if (ret)
+ return dev_err_probe(dev, ret, "failed to add clock provider\n");
+
+ platform_set_drvdata(pdev, (void *)desc);
+
+ return rtk_reset_controller_register(dev, desc->aux_name, regmap);
+}
+EXPORT_SYMBOL_NS_GPL(rtk_clk_probe, "CLK_REALTEK");
+
+void rtk_clk_remove(struct platform_device *pdev)
+{
+ const struct rtk_clk_desc *desc = platform_get_drvdata(pdev);
+
+ if (!desc)
+ return;
+
+ for (int i = 0; i < desc->num_clks; i++)
+ desc->clks[i]->regmap = NULL;
+}
+EXPORT_SYMBOL_NS_GPL(rtk_clk_remove, "CLK_REALTEK");
+
+MODULE_DESCRIPTION("Realtek clock infrastructure");
+MODULE_LICENSE("GPL");
diff --git a/drivers/clk/realtek/clk-rtk-common.h b/drivers/clk/realtek/clk-rtk-common.h
new file mode 100644
index 000000000000..87a0ff8729d5
--- /dev/null
+++ b/drivers/clk/realtek/clk-rtk-common.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Copyright (C) 2016-2026 Realtek Semiconductor Corporation
+ * Author: Cheng-Yu Lee <cylee12@realtek.com>
+ */
+
+#ifndef __CLK_REALTEK_COMMON_H
+#define __CLK_REALTEK_COMMON_H
+
+#include <linux/clk-provider.h>
+
+#define __rtk_clk_regmap_hw(_p) ((_p)->hw)
+
+struct device;
+struct platform_device;
+struct regmap;
+
+struct rtk_clk_regmap {
+ struct clk_hw hw;
+ struct regmap *regmap;
+};
+
+struct rtk_clk_desc {
+ struct clk_hw_onecell_data *clk_data;
+ struct rtk_clk_regmap **clks;
+ size_t num_clks;
+ char *aux_name;
+};
+
+static inline struct rtk_clk_regmap *to_rtk_clk_regmap(struct clk_hw *hw)
+{
+ return container_of(hw, struct rtk_clk_regmap, hw);
+}
+
+int rtk_clk_probe(struct platform_device *pdev, const struct rtk_clk_desc *desc);
+void rtk_clk_remove(struct platform_device *pdev);
+
+#endif /* __CLK_REALTEK_COMMON_H */
--
2.43.0
next prev parent reply other threads:[~2026-08-04 16:39 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-04 16:37 [PATCH v12 00/11] clk / reset: realtek: Add RTD1625 clock and reset support Yu-Chun Lin
2026-08-04 16:37 ` [PATCH v12 01/11] dt-bindings: clock: Add Realtek RTD1625 Clock & Reset Controller Yu-Chun Lin
2026-08-04 16:37 ` [PATCH v12 02/11] reset: Add Realtek basic reset support Yu-Chun Lin
2026-08-04 16:37 ` [PATCH v12 03/11] reset: realtek: Add RTD1625 reset controller driver Yu-Chun Lin
2026-08-04 16:38 ` Yu-Chun Lin [this message]
2026-08-04 16:38 ` [PATCH v12 05/11] clk: realtek: Add support for phase locked loops (PLLs) Yu-Chun Lin
2026-08-04 16:38 ` [PATCH v12 06/11] clk: realtek: Add support for gate clock Yu-Chun Lin
2026-08-04 16:38 ` [PATCH v12 07/11] clk: realtek: Add support for mux clock Yu-Chun Lin
2026-08-04 16:38 ` [PATCH v12 08/11] clk: realtek: Add support for MMC-tuned PLL clocks Yu-Chun Lin
2026-08-04 16:38 ` [PATCH v12 09/11] clk: realtek: Add RTD1625-CRT clock controller driver Yu-Chun Lin
2026-08-04 16:38 ` [PATCH v12 10/11] clk: realtek: Add RTD1625-ISO " Yu-Chun Lin
2026-08-04 16:38 ` [PATCH v12 11/11] arm64: dts: realtek: Add clock support for RTD1625 Yu-Chun Lin
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