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Add clk_regmap_gate_ro_ops as a read-only variant exposing only is_enabled. Reviewed-by: Brian Masney Signed-off-by: Cheng-Yu Lee Co-developed-by: Yu-Chun Lin Signed-off-by: Yu-Chun Lin --- Changes in v12: - Add Reviewed-by tag from Brian. - Change 'gate_ofs' type to 'unsigned int'. --- drivers/clk/realtek/Makefile | 1 + drivers/clk/realtek/clk-regmap-gate.c | 70 +++++++++++++++++++++++++++ drivers/clk/realtek/clk-regmap-gate.h | 65 +++++++++++++++++++++++++ 3 files changed, 136 insertions(+) create mode 100644 drivers/clk/realtek/clk-regmap-gate.c create mode 100644 drivers/clk/realtek/clk-regmap-gate.h diff --git a/drivers/clk/realtek/Makefile b/drivers/clk/realtek/Makefile index 71edc18121c6..840aff067b61 100644 --- a/drivers/clk/realtek/Makefile +++ b/drivers/clk/realtek/Makefile @@ -3,4 +3,5 @@ obj-$(CONFIG_RTK_CLK_COMMON) += clk-rtk.o clk-rtk-y += clk-rtk-common.o clk-rtk-y += clk-pll.o +clk-rtk-y += clk-regmap-gate.o clk-rtk-y += freq_table.o diff --git a/drivers/clk/realtek/clk-regmap-gate.c b/drivers/clk/realtek/clk-regmap-gate.c new file mode 100644 index 000000000000..1c32a87d97df --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.c @@ -0,0 +1,70 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#include +#include +#include +#include +#include "clk-regmap-gate.h" + +static int rtk_clk_regmap_gate_enable(struct clk_hw *hw) +{ + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask = BIT(clkg->bit_idx); + val = BIT(clkg->bit_idx); + + if (clkg->write_en) { + mask |= BIT(clkg->bit_idx + 1); + val |= BIT(clkg->bit_idx + 1); + } + + return regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static void rtk_clk_regmap_gate_disable(struct clk_hw *hw) +{ + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); + unsigned int mask; + unsigned int val; + + mask = BIT(clkg->bit_idx); + val = 0; + + if (clkg->write_en) { + mask |= BIT(clkg->bit_idx + 1); + val |= BIT(clkg->bit_idx + 1); + } + + regmap_update_bits(clkg->clkr.regmap, clkg->gate_ofs, mask, val); +} + +static int rtk_clk_regmap_gate_is_enabled(struct clk_hw *hw) +{ + struct rtk_clk_regmap_gate *clkg = to_rtk_clk_regmap_gate(hw); + int ret; + u32 val; + + ret = regmap_read(clkg->clkr.regmap, clkg->gate_ofs, &val); + if (ret < 0) + return ret; + + return !!(val & BIT(clkg->bit_idx)); +} + +const struct clk_ops rtk_clk_regmap_gate_ops = { + .enable = rtk_clk_regmap_gate_enable, + .disable = rtk_clk_regmap_gate_disable, + .is_enabled = rtk_clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ops, "CLK_REALTEK"); + +const struct clk_ops rtk_clk_regmap_gate_ro_ops = { + .is_enabled = rtk_clk_regmap_gate_is_enabled, +}; +EXPORT_SYMBOL_NS_GPL(rtk_clk_regmap_gate_ro_ops, "CLK_REALTEK"); diff --git a/drivers/clk/realtek/clk-regmap-gate.h b/drivers/clk/realtek/clk-regmap-gate.h new file mode 100644 index 000000000000..9303adda3166 --- /dev/null +++ b/drivers/clk/realtek/clk-regmap-gate.h @@ -0,0 +1,65 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2017-2026 Realtek Semiconductor Corporation + * Author: Cheng-Yu Lee + */ + +#ifndef __CLK_REALTEK_CLK_REGMAP_GATE_H +#define __CLK_REALTEK_CLK_REGMAP_GATE_H + +#include "clk-rtk-common.h" + +struct rtk_clk_regmap_gate { + struct rtk_clk_regmap clkr; + unsigned int gate_ofs; + u8 bit_idx; + u32 write_en : 1; +}; + +#define __rtk_clk_regmap_gate_hw(_p) __rtk_clk_regmap_hw(&(_p)->clkr) + +#define __RTK_CLK_REGMAP_GATE(_name, _parent, _ops, _flags, _ofs, _bit_idx, \ + _write_en) \ + struct rtk_clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT(#_name, _parent, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ + } + +#define RTK_CLK_REGMAP_GATE(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ops, _flags, _ofs, \ + _bit_idx, _write_en) + +#define RTK_CLK_REGMAP_GATE_RO(_name, _parent, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE(_name, _parent, &rtk_clk_regmap_gate_ro_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +#define __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, _ops, _flags, _ofs, _bit_idx, \ + _write_en) \ + struct rtk_clk_regmap_gate _name = { \ + .clkr.hw.init = CLK_HW_INIT_NO_PARENT(#_name, _ops, _flags), \ + .gate_ofs = _ofs, \ + .bit_idx = _bit_idx, \ + .write_en = _write_en, \ + } + +#define RTK_CLK_REGMAP_GATE_NO_PARENT(_name, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ops, _flags, _ofs, \ + _bit_idx, _write_en) + +#define RTK_CLK_REGMAP_GATE_NO_PARENT_RO(_name, _flags, _ofs, _bit_idx, _write_en) \ + __RTK_CLK_REGMAP_GATE_NO_PARENT(_name, &rtk_clk_regmap_gate_ro_ops, _flags, \ + _ofs, _bit_idx, _write_en) + +static inline struct rtk_clk_regmap_gate *to_rtk_clk_regmap_gate(struct clk_hw *hw) +{ + struct rtk_clk_regmap *clkr = to_rtk_clk_regmap(hw); + + return container_of(clkr, struct rtk_clk_regmap_gate, clkr); +} + +extern const struct clk_ops rtk_clk_regmap_gate_ops; +extern const struct clk_ops rtk_clk_regmap_gate_ro_ops; + +#endif /* __CLK_REALTEK_CLK_REGMAP_GATE_H */ -- 2.43.0