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[79.42.255.151]) by smtp.googlemail.com with ESMTPSA id ffacd0b85a97d-47ff79a7f07sm8070586f8f.8.2026.08.06.09.53.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Aug 2026 09:53:44 -0700 (PDT) From: Christian Marangi To: Lorenzo Pieralisi , =?UTF-8?q?Krzysztof=20Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Krzysztof Kozlowski , Conor Dooley , Ryder Lee , Philipp Zabel , Matthias Brugger , AngeloGioacchino Del Regno , Christian Marangi , Jianjun Wang , linux-pci@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v5 1/2] dt-bindings: PCI: mediatek-gen3: Split Airoha schema and document 2-lanes Date: Thu, 6 Aug 2026 18:53:31 +0200 Message-ID: <20260806165334.7328-2-ansuelsmth@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20260806165334.7328-1-ansuelsmth@gmail.com> References: <20260806165334.7328-1-ansuelsmth@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260806_095347_445411_F11914C1 X-CRM114-Status: GOOD ( 19.66 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org To permit proper documentation of required property to support PCIe configured for 2-lanes mode, split the Airoha schema part from the mediatek-gen3 schema to a dedicated schema. A PCIe configured for 2-lanes mode require an additional reg for the secondary PCIe to be configured and the airoha,scu phandle to correctly configure the PCIe MUX. Rework the mediatek-gen3 schema to drop any redundant constraint previsouly introduced for Airoha PCIe properties. Signed-off-by: Christian Marangi Reviewed-by: Rob Herring (Arm) --- .../bindings/pci/airoha,en7581-pcie.yaml | 244 ++++++++++++++++++ .../bindings/pci/mediatek-pcie-gen3.yaml | 77 +----- 2 files changed, 249 insertions(+), 72 deletions(-) create mode 100644 Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml b/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml new file mode 100644 index 000000000000..78a181a3b599 --- /dev/null +++ b/Documentation/devicetree/bindings/pci/airoha,en7581-pcie.yaml @@ -0,0 +1,244 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/airoha,en7581-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Gen3 PCIe controller on Airoha SoCs + +maintainers: + - Christian Marangi + +description: |+ + PCIe Gen3 MAC controller for Airoha SoCs, it supports Gen3 speed + and compatible with Gen2, Gen1 speed. + + This PCIe controller supports up to 256 MSI vectors, the MSI hardware + block diagram is as follows: + + +-----+ + | GIC | + +-----+ + ^ + | + port->irq + | + +-+-+-+-+-+-+-+-+ + |0|1|2|3|4|5|6|7| (PCIe intc) + +-+-+-+-+-+-+-+-+ + ^ ^ ^ + | | ... | + +-------+ +------+ +-----------+ + | | | + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ + |0|1|...|30|31| |0|1|...|30|31| |0|1|...|30|31| (MSI sets) + +-+-+---+--+--+ +-+-+---+--+--+ +-+-+---+--+--+ + ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ + | | | | | | | | | | | | (MSI vectors) + | | | | | | | | | | | | + + (MSI SET0) (MSI SET1) ... (MSI SET7) + + With 256 MSI vectors supported, the MSI vectors are composed of 8 sets, + each set has its own address for MSI message, and supports 32 MSI vectors + to generate interrupt. + +properties: + compatible: + const: airoha,en7581-pcie + + reg: + minItems: 1 + maxItems: 2 + + reg-names: + minItems: 1 + maxItems: 2 + + interrupts: + maxItems: 1 + + ranges: + maxItems: 1 + + resets: + minItems: 1 + maxItems: 4 + + reset-names: + minItems: 1 + maxItems: 4 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: sys-ck + + phys: + maxItems: 1 + + phy-names: + items: + - const: pcie-phy + + num-lanes: + enum: [1, 2] + + mediatek,pbus-csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to pbus-csr syscon + - description: offset of pbus-csr base address register + - description: offset of pbus-csr base address mask register + description: + Phandle with two arguments to the syscon node used to detect if + a given address is accessible on PCIe controller. + + airoha,scu: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to airoha SCU syscon + description: + Phandle to SCU syscon to configure PCIe MUX for 2 lines support. + + '#interrupt-cells': + const: 1 + + interrupt-controller: + description: Interrupt controller node for handling INTx PCI interrupts. + type: object + properties: + '#address-cells': + const: 0 + '#interrupt-cells': + const: 1 + interrupt-controller: true + + required: + - '#address-cells' + - '#interrupt-cells' + - interrupt-controller + + additionalProperties: false + +required: + - compatible + - reg + - reg-names + - interrupts + - ranges + - clocks + - clock-names + - '#interrupt-cells' + - interrupt-controller + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + - if: + properties: + num-lanes: + const: 2 + then: + properties: + reg: + minItems: 2 + + reg-names: + items: + - const: pcie-mac + - const: sec-pcie-mac + + resets: + minItems: 4 + + reset-names: + items: + - const: phy-lane0 + - const: phy-lane1 + - const: perstout + - const: sec-perstout + + required: + - airoha,scu + + else: + properties: + reg: + maxItems: 1 + + reg-names: + items: + - const: pcie-mac + + resets: + minItems: 2 + maxItems: 3 + + reset-names: + minItems: 2 + items: + - enum: [ phy-lane0, phy-lane1, phy-lane2 ] + - enum: [ phy-lane1, perstout ] + - const: phy-lane2 + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells = <2>; + #size-cells = <2>; + + pcie@1fc00000 { + compatible = "airoha,en7581-pcie"; + device_type = "pci"; + #address-cells = <3>; + #size-cells = <2>; + + reg = <0x0 0x1fc00000 0x0 0x1670>, + <0x0 0x1fc20000 0x0 0x1670>; + reg-names = "pcie-mac", "sec-pcie-mac"; + + clocks = <&scuclk 7>; + clock-names = "sys-ck"; + + phys = <&pciephy>; + phy-names = "pcie-phy"; + + ranges = <0x02000000 0 0x20000000 0x0 0x20000000 0 0x4000000>; + + resets = <&scuclk 48>, + <&scuclk 49>, + <&scuclk 53>, + <&scuclk 54>; + reset-names = "phy-lane0", "phy-lane1", + "perstout", "sec-perstout"; + + num-lanes = <2>; + + mediatek,pbus-csr = <&pbus_csr 0x0 0x4>; + + airoha,scu = <&scuclk>; + + interrupts = ; + bus-range = <0x00 0xff>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 0x7>; + interrupt-map = <0 0 0 1 &pcie_intc 0>, + <0 0 0 2 &pcie_intc 1>, + <0 0 0 3 &pcie_intc 2>, + <0 0 0 4 &pcie_intc 3>; + pcie_intc: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml index 4db700fc36ba..510f1f2b1c5a 100644 --- a/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml +++ b/Documentation/devicetree/bindings/pci/mediatek-pcie-gen3.yaml @@ -59,7 +59,6 @@ properties: - const: mediatek,mt8196-pcie - const: mediatek,mt8192-pcie - const: mediatek,mt8196-pcie - - const: airoha,en7581-pcie reg: maxItems: 1 @@ -83,20 +82,20 @@ properties: resets: minItems: 1 - maxItems: 3 + maxItems: 2 reset-names: minItems: 1 - maxItems: 3 + maxItems: 2 items: - enum: [ phy, mac, phy-lane0, phy-lane1, phy-lane2 ] + enum: [ phy, mac ] clocks: - minItems: 1 + minItems: 4 maxItems: 6 clock-names: - minItems: 1 + minItems: 4 maxItems: 6 assigned-clocks: @@ -115,17 +114,6 @@ properties: power-domains: maxItems: 1 - mediatek,pbus-csr: - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - - items: - - description: phandle to pbus-csr syscon - - description: offset of pbus-csr base address register - - description: offset of pbus-csr base address mask register - description: - Phandle with two arguments to the syscon node used to detect if - a given address is accessible on PCIe controller. - '#interrupt-cells': const: 1 @@ -177,16 +165,6 @@ allOf: - const: peri_26m - const: top_133m - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - if: properties: compatible: @@ -208,16 +186,6 @@ allOf: - const: peri_26m - const: peri_mem - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - if: properties: compatible: @@ -246,8 +214,6 @@ allOf: - const: phy - const: mac - mediatek,pbus-csr: false - - if: properties: compatible: @@ -257,7 +223,6 @@ allOf: then: properties: clocks: - minItems: 4 maxItems: 4 clock-names: @@ -267,38 +232,6 @@ allOf: - const: peri_26m - const: top_133m - resets: - minItems: 1 - maxItems: 2 - - reset-names: - minItems: 1 - maxItems: 2 - - mediatek,pbus-csr: false - - - if: - properties: - compatible: - const: airoha,en7581-pcie - then: - properties: - clocks: - maxItems: 1 - - clock-names: - items: - - const: sys-ck - - resets: - minItems: 3 - - reset-names: - items: - - const: phy-lane0 - - const: phy-lane1 - - const: phy-lane2 - unevaluatedProperties: false examples: -- 2.53.0