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From: Atish Patra <atish.patra@linux.dev>
To: Will Deacon <will@kernel.org>,
	Atish Patra <atish.patra@linux.dev>,
	 Arnaldo Carvalho de Melo <acme@kernel.org>,
	 Anup Patel <anup@brainfault.org>,
	Ian Rogers <irogers@google.com>,  Rob Herring <robh@kernel.org>,
	Paul Walmsley <pjw@kernel.org>,
	 Mark Rutland <mark.rutland@arm.com>,
	Jiri Olsa <jolsa@kernel.org>,
	 Krzysztof Kozlowski <krzk+dt@kernel.org>,
	 James Clark <james.clark@linaro.org>,
	Namhyung Kim <namhyung@kernel.org>
Cc: linux-riscv@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	 Conor Dooley <conor@kernel.org>,
	linux-kernel@vger.kernel.org,  linux-perf-users@vger.kernel.org,
	devicetree@vger.kernel.org
Subject: [PATCH v9 19/20] tools/perf: Support event code for arch standard events
Date: Fri, 07 Aug 2026 01:09:14 -0700	[thread overview]
Message-ID: <20260807-counter_delegation-v9-19-58658104e487@meta.com> (raw)
In-Reply-To: <20260807-counter_delegation-v9-0-58658104e487@meta.com>

From: Atish Patra <atishp@rivosinc.com>

RISC-V relies on the event encoding from the json file. That includes
arch standard events. If event code is present, event is already updated
with correct encoding. No need to update it again which results in losing
the event encoding.

Signed-off-by: Atish Patra <atishp@rivosinc.com>
Reviewed-by: Ian Rogers <irogers@google.com>
---
 tools/perf/pmu-events/arch/riscv/arch-standard.json | 10 ++++++++++
 tools/perf/pmu-events/jevents.py                    |  9 ++++++++-
 2 files changed, 18 insertions(+), 1 deletion(-)

diff --git a/tools/perf/pmu-events/arch/riscv/arch-standard.json b/tools/perf/pmu-events/arch/riscv/arch-standard.json
new file mode 100644
index 000000000000..96e21f088558
--- /dev/null
+++ b/tools/perf/pmu-events/arch/riscv/arch-standard.json
@@ -0,0 +1,10 @@
+[
+  {
+    "EventName": "cycles",
+    "BriefDescription": "cycle executed"
+  },
+  {
+    "EventName": "instructions",
+    "BriefDescription": "instruction retired"
+  }
+]
diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
index 376dc2d24162..e9c6b7990880 100755
--- a/tools/perf/pmu-events/jevents.py
+++ b/tools/perf/pmu-events/jevents.py
@@ -413,7 +413,14 @@ class JsonEvent:
         self.long_desc = None
     if arch_std:
       if arch_std.lower() in _arch_std_events:
-        event = _arch_std_events[arch_std.lower()].event
+        # Inherit the arch-standard encoding only if this event defines no
+        # explicit encoding of its own. Events with explicit EventCode,
+        # ConfigCode, etc. may carry alternate encodings and appended modifiers
+        # that must survive.
+        if ('EventCode' not in jd and 'ExtSel' not in jd and
+            configcode is None and eventidcode is None and
+            legacy_hw_config is None and legacy_cache_config is None):
+          event = _arch_std_events[arch_std.lower()].event
         # Copy from the architecture standard event to self for undefined fields.
         for attr, value in _arch_std_events[arch_std.lower()].__dict__.items():
           if hasattr(self, attr) and not getattr(self, attr):

-- 
2.53.0-Meta



  parent reply	other threads:[~2026-08-07  8:10 UTC|newest]

Thread overview: 21+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-07  8:08 [PATCH v9 00/20] Add Counter delegation ISA extension support Atish Patra
2026-08-07  8:08 ` [PATCH v9 01/20] RISC-V: perf: fix resource cleanup on driver probe failure Atish Patra
2026-08-07  8:08 ` [PATCH v9 02/20] RISC-V: Add Smcsrind and Sscsrind ISA extension CSR definitions Atish Patra
2026-08-07  8:08 ` [PATCH v9 03/20] RISC-V: Add Smcsrind and Sscsrind ISA extension definition and parsing Atish Patra
2026-08-07  8:08 ` [PATCH v9 04/20] dt-bindings: riscv: add Smcsrind and Sscsrind ISA extension descriptions Atish Patra
2026-08-07  8:09 ` [PATCH v9 05/20] RISC-V: Define indirect CSR access helpers Atish Patra
2026-08-07  8:09 ` [PATCH v9 06/20] RISC-V: Add Smcntrpmf extension parsing Atish Patra
2026-08-07  8:09 ` [PATCH v9 07/20] dt-bindings: riscv: add Smcntrpmf ISA extension description Atish Patra
2026-08-07  8:09 ` [PATCH v9 08/20] RISC-V: Add Ssccfg extension CSR definition Atish Patra
2026-08-07  8:09 ` [PATCH v9 09/20] RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing Atish Patra
2026-08-07  8:09 ` [PATCH v9 10/20] dt-bindings: riscv: add Counter delegation ISA extensions description Atish Patra
2026-08-07  8:09 ` [PATCH v9 11/20] RISC-V: perf: Restructure the SBI PMU code Atish Patra
2026-08-07  8:09 ` [PATCH v9 12/20] RISC-V: perf: Modify the counter discovery mechanism Atish Patra
2026-08-07  8:09 ` [PATCH v9 13/20] RISC-V: perf: Add a mechanism to defined legacy event encoding Atish Patra
2026-08-07  8:09 ` [PATCH v9 14/20] RISC-V: perf: Implement supervisor counter delegation support Atish Patra
2026-08-07  8:09 ` [PATCH v9 15/20] RISC-V: perf: Skip PMU SBI extension when not implemented Atish Patra
2026-08-07  8:09 ` [PATCH v9 16/20] RISC-V: perf: Use config2/vendor table for event to counter mapping Atish Patra
2026-08-07  8:09 ` [PATCH v9 17/20] RISC-V: perf: Add legacy event encodings via sysfs Atish Patra
2026-08-07  8:09 ` [PATCH v9 18/20] RISC-V: perf: Add Qemu virt machine events Atish Patra
2026-08-07  8:09 ` Atish Patra [this message]
2026-08-07  8:09 ` [PATCH v9 20/20] tools/perf: Add RISC-V CounterIDMask event field Atish Patra

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