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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: IyMHHDHesOklomZEJ4WKz8FNJmxhn6xyw8z0g3Op8oOF9t3bNo5LPzA/a8zeH4AeaunWaImEaKnTojQiV39kgzIk+hu9/QTktdUPiFbel716FC70Ghk9qIt85nN4AY6MnwLWdfRgrlqBKeRg7/h8+KwRzjThw5I4jEhJzSe3VOo92X2Qi34nRZ+lP1WyYoW9aSPOiwApAaF4H6LwVTeTrv4+9acumONVNXb+YumERjDVTJCbFJXfxmpiB4CZILSFmr6O2F43rNvEKGbBsqnMSzo9eqmdINUnZda3OAHkzBOHJNCpi9oP0sHSytNbl4S5pUCmscstehe0vVveQkFJTkFyH8Zb83dCYCSoAL0yqOvChYlibqKlHUudn2RZntPAbh/FO4x3337BeBnVY74oWo+hQfkV6AMi7veqoMzpOMOMmpLU8rMFXqNsulFq1yi2 X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 07 Aug 2026 11:28:25.6797 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: b9c3cbbd-c41d-42aa-9af0-08def476ff30 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[4.158.2.129];Helo=[outbound-uk1.az.dlp.m.darktrace.com] X-MS-Exchange-CrossTenant-AuthSource: DU2PEPF00028D0F.eurprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DU0PR08MB7810 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.9.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20260807_042833_111505_F6E98586 X-CRM114-Status: GOOD ( 19.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Only a subset of the possible PPIs are exposed to a guest when running with a vGICv5. First of all, only the architected PPIs are considered by KVM. Secondly, only a set of those is exposed to a guest: those corresponding to devices that KVM emulates, such as the timers and PMU, and the GICv5 SW_PPI. The finalisation of exposed PPIs happens on first vCPU run, as this is the first time when the full set of exposed devices is known. At this stage a mask is calculated, and this mask is applied both to hide non-exposed PPI state from the guest and to reduce overhead when iterating over the PPIs. While preparing userspace access to the GICv5 system registers, it became apparent that restoring the GICv5 PPI registers can result in a mismatch between the state supplied by userspace and the state KVM intends to expose. Userspace can provide Enable, Active, and Pending state for PPIs that KVM has chosen to hide from the guest. Userspace must restore PPI state before any vCPU runs. The userspace access path added subsequently enforces this ordering. Rework vgic_v5_finalize_ppi_state() to calculate the mask of exposed PPIs and clear any state belonging to non-exposed PPIs. This ensures that only the state KVM intends to expose is visible to the guest. Signed-off-by: Sascha Bischoff --- arch/arm64/kvm/arm.c | 2 +- arch/arm64/kvm/vgic/vgic-v5.c | 71 +++++++++++++++++++++++++---------- include/kvm/arm_vgic.h | 2 +- 3 files changed, 53 insertions(+), 22 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index 908a058314117..c56e2a007b2e7 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -974,7 +974,7 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) return ret; } =20 - ret =3D vgic_v5_finalize_ppi_state(kvm); + ret =3D vgic_v5_finalize_ppi_state(vcpu); if (ret) return ret; =20 diff --git a/arch/arm64/kvm/vgic/vgic-v5.c b/arch/arm64/kvm/vgic/vgic-v5.c index 62e069c21367a..beabc5980b2c1 100644 --- a/arch/arm64/kvm/vgic/vgic-v5.c +++ b/arch/arm64/kvm/vgic/vgic-v5.c @@ -781,9 +781,10 @@ int vgic_v5_map_resources(struct kvm *kvm) return 0; } =20 -int vgic_v5_finalize_ppi_state(struct kvm *kvm) +int vgic_v5_finalize_ppi_state(struct kvm_vcpu *vcpu) { - struct kvm_vcpu *vcpu0; + struct kvm *kvm =3D vcpu->kvm; + struct vgic_v5_cpu_if *cpu_if =3D &vcpu->arch.vgic_cpu.vgic_v5; int i; =20 if (!vgic_is_v5(kvm)) @@ -792,35 +793,65 @@ int vgic_v5_finalize_ppi_state(struct kvm *kvm) guard(mutex)(&kvm->arch.config_lock); =20 /* - * If SW_PPI has been advertised, then we know we already - * initialised the whole thing, and we can return early. Yes, - * this is pretty hackish as far as state tracking goes... + * Discover the set of PPIs that are exposed to the guest once per VM. + * Once known, apply that mask to each VCPU's restored PPI state as the + * VCPUs are first run. */ - if (test_bit(GICV5_ARCH_PPI_SW_PPI, kvm->arch.vgic.gicv5_vm.vgic_ppi_mask= )) - return 0; - - /* The PPI state for all VCPUs should be the same. Pick the first. */ - vcpu0 =3D kvm_get_vcpu(kvm, 0); + if (!test_bit(GICV5_ARCH_PPI_SW_PPI, kvm->arch.vgic.gicv5_vm.vgic_ppi_mas= k)) { + bitmap_zero(kvm->arch.vgic.gicv5_vm.vgic_ppi_mask, + VGIC_V5_NR_PRIVATE_IRQS); + bitmap_zero(kvm->arch.vgic.gicv5_vm.vgic_ppi_hmr, + VGIC_V5_NR_PRIVATE_IRQS); + + for_each_set_bit(i, ppi_caps.impl_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS) { + const u32 intid =3D vgic_v5_make_ppi(i); + struct vgic_irq *irq; + + irq =3D vgic_get_vcpu_irq(vcpu, intid); + + /* Expose PPIs with an owner or the SW_PPI, only */ + scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) { + if (irq->owner || i =3D=3D GICV5_ARCH_PPI_SW_PPI) { + __set_bit(i, kvm->arch.vgic.gicv5_vm.vgic_ppi_mask); + __assign_bit(i, kvm->arch.vgic.gicv5_vm.vgic_ppi_hmr, + irq->config =3D=3D VGIC_CONFIG_LEVEL); + } + } =20 - bitmap_zero(kvm->arch.vgic.gicv5_vm.vgic_ppi_mask, VGIC_V5_NR_PRIVATE_IRQ= S); - bitmap_zero(kvm->arch.vgic.gicv5_vm.vgic_ppi_hmr, VGIC_V5_NR_PRIVATE_IRQS= ); + vgic_put_irq(kvm, irq); + } + } =20 - for_each_set_bit(i, ppi_caps.impl_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS) { + /* + * Apply the mask to Enable, Active. Skip pending as that's calculated + * on guest entry. + */ + bitmap_and(cpu_if->vgic_ppi_enabler, cpu_if->vgic_ppi_enabler, + kvm->arch.vgic.gicv5_vm.vgic_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS); + bitmap_and(cpu_if->vgic_ppi_activer, cpu_if->vgic_ppi_activer, + kvm->arch.vgic.gicv5_vm.vgic_ppi_mask, VGIC_V5_NR_PRIVATE_IRQS); + + /* Also update the vgic_irqs */ + for (i =3D 0; i < VGIC_V5_NR_PRIVATE_IRQS; i++) { + bool visible =3D test_bit(i, kvm->arch.vgic.gicv5_vm.vgic_ppi_mask); const u32 intid =3D vgic_v5_make_ppi(i); struct vgic_irq *irq; =20 - irq =3D vgic_get_vcpu_irq(vcpu0, intid); + irq =3D vgic_get_vcpu_irq(vcpu, intid); =20 - /* Expose PPIs with an owner or the SW_PPI, only */ scoped_guard(raw_spinlock_irqsave, &irq->irq_lock) { - if (irq->owner || i =3D=3D GICV5_ARCH_PPI_SW_PPI) { - __set_bit(i, kvm->arch.vgic.gicv5_vm.vgic_ppi_mask); - __assign_bit(i, kvm->arch.vgic.gicv5_vm.vgic_ppi_hmr, - irq->config =3D=3D VGIC_CONFIG_LEVEL); + if (!visible) { + irq->enabled =3D false; + irq->active =3D false; + irq->pending_latch =3D false; + irq->line_level =3D false; + } else { + irq->enabled =3D test_bit(i, cpu_if->vgic_ppi_enabler); + irq->active =3D test_bit(i, cpu_if->vgic_ppi_activer); } } =20 - vgic_put_irq(vcpu0->kvm, irq); + vgic_put_irq(kvm, irq); } =20 return 0; diff --git a/include/kvm/arm_vgic.h b/include/kvm/arm_vgic.h index 9f16ee63d5763..b6526c678a5a2 100644 --- a/include/kvm/arm_vgic.h +++ b/include/kvm/arm_vgic.h @@ -823,7 +823,7 @@ static inline u32 vgic_v5_irs_max_vpes(const struct vgi= c_v5_irs_caps *caps) return BIT(FIELD_GET(GICV5_IRS_IDR4_VPE_ID_BITS, caps->idr4) + 1); } =20 -int vgic_v5_finalize_ppi_state(struct kvm *kvm); +int vgic_v5_finalize_ppi_state(struct kvm_vcpu *vcpu); bool vgic_v5_ppi_queue_irq_unlock(struct kvm *kvm, struct vgic_irq *irq, unsigned long flags); void vgic_v5_set_ppi_dvi(struct kvm_vcpu *vcpu, struct vgic_irq *irq, bool= dvi); --=20 2.34.1