From: Sascha Bischoff <Sascha.Bischoff@arm.com>
To: "linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>,
"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Cc: nd <nd@arm.com>, "maz@kernel.org" <maz@kernel.org>,
"oupton@kernel.org" <oupton@kernel.org>,
Joey Gouly <Joey.Gouly@arm.com>,
Suzuki Poulose <Suzuki.Poulose@arm.com>,
"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
"lpieralisi@kernel.org" <lpieralisi@kernel.org>
Subject: [PATCH 0/5] arm64: gic-v5: Fixes from GICv5 KVM IRS review
Date: Mon, 10 Aug 2026 10:27:06 +0000 [thread overview]
Message-ID: <20260810102652.758719-1-sascha.bischoff@arm.com> (raw)
Hi all,
While reviewing v4 of the KVM GICv5 IRS series [1], Sashiko [2]
identified a number of issues in GICv5 and vGIC code that has already
been merged. This series contains the fixes for these issues.
The fixes are:
* Free gic_kvm_info when vGIC initialisation fails because the
maintenance interrupt is not provided but is required. This routes
the failure through the existing cleanup path to free gic_kvm_info
again.
* Clear the per-CPU IRS pointer and IAFFID state when host IRS
initialisation fails or an IRS is removed. This prevents the per-CPU
state from retaining a pointer to freed IRS data, thereby avoiding a
potential deference of a stale pointer later on.
* Add an isb() after disabling the GICv5 CPU interface. This ensures
that interrupts are disabled before the helper returns.
* Fix speculative accesses in the common vGIC SPI lookup which could
previously underflow. The SPI index is now made relative to the SPI
array before array_index_nospec() constrains it rather than
afterwards.
* Reject GICv5 PPIs outside KVM's supported private IRQ range. These
were previously clamped to zero, and hence would alias private IRQ 0
for an out-of-range PPI ID.
These changes are based on v7.2-rc7.
Thanks,
Sascha
[1] https://lore.kernel.org/all/20260724104819.1296803-1-sascha.bischoff@arm.com/
[2] https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff%40arm.com
Sascha Bischoff (5):
KVM: arm64: vgic: Free gic_kvm_info on initialization failure
irqchip/gic-v5: Clear per-CPU IRS data on teardown
irqchip/gic-v5: Synchronize CPU interface disable
KVM: arm64: vgic: Prevent speculative SPI array underflow
KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs
arch/arm64/kvm/vgic/vgic-init.c | 4 +++-
arch/arm64/kvm/vgic/vgic.c | 7 +++++--
drivers/irqchip/irq-gic-v5-irs.c | 16 ++++++++++++++++
drivers/irqchip/irq-gic-v5.c | 1 +
4 files changed, 25 insertions(+), 3 deletions(-)
--
2.34.1
next reply other threads:[~2026-08-10 10:28 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-08-10 10:27 Sascha Bischoff [this message]
2026-08-10 10:27 ` [PATCH 1/5] KVM: arm64: vgic: Free gic_kvm_info on initialization failure Sascha Bischoff
2026-08-10 10:28 ` [PATCH 2/5] irqchip/gic-v5: Clear per-CPU IRS data on teardown Sascha Bischoff
2026-08-10 11:36 ` Lorenzo Pieralisi
2026-08-10 10:28 ` [PATCH 3/5] irqchip/gic-v5: Synchronize CPU interface disable Sascha Bischoff
2026-08-10 10:29 ` [PATCH 4/5] KVM: arm64: vgic: Prevent speculative SPI array underflow Sascha Bischoff
2026-08-10 10:29 ` [PATCH 5/5] KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs Sascha Bischoff
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