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From: Sascha Bischoff <Sascha.Bischoff@arm.com>
To: "linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"kvmarm@lists.linux.dev" <kvmarm@lists.linux.dev>,
	"kvm@vger.kernel.org" <kvm@vger.kernel.org>
Cc: nd <nd@arm.com>, "maz@kernel.org" <maz@kernel.org>,
	"oupton@kernel.org" <oupton@kernel.org>,
	Joey Gouly <Joey.Gouly@arm.com>,
	Suzuki Poulose <Suzuki.Poulose@arm.com>,
	"yuzenghui@huawei.com" <yuzenghui@huawei.com>,
	"lpieralisi@kernel.org" <lpieralisi@kernel.org>
Subject: [PATCH v2 0/4] KVM: arm64: GICv5 KVM IRS review fixes
Date: Tue, 11 Aug 2026 15:09:46 +0000	[thread overview]
Message-ID: <20260811150941.941295-1-sascha.bischoff@arm.com> (raw)

Hi all,

v1 [1] combined irqchip and KVM fixes identified by Sashiko [2] while
reviewing the GICv5 KVM IRS series [3]. Following feedback, v2 splits
the fixes into separate irqchip and KVM postings. This posting
contains the KVM fixes; the irqchip fixes are posted separately.

Changes since v1:

* Split the combined series into irqchip and KVM postings.

* Extend the out-of-range GICv5 PPI fix to reject unsupported PPIs at
  the type-validation boundary as well as in the lookup path.

* Add a fix to validate a GICv5 timer PPI before claiming its IRQ.

The fixes are:

* Free gic_kvm_info when vGIC initialisation fails because the
  maintenance interrupt is not provided but is required.

* Fix speculative accesses in the common vGIC SPI lookup which could
  previously underflow. The SPI index is now made relative to the SPI
  array before array_index_nospec() constrains it rather than
  afterwards.

* Reject GICv5 PPIs outside KVM's supported private IRQ range. These
  were previously classified as PPIs and clamped to zero, aliasing
  private IRQ 0.

* Validate the architecturally fixed GICv5 timer PPI before claiming it
  with the vGIC.

These changes are based on v7.2-rc7.

Thanks,
Sascha

[1] https://lore.kernel.org/all/20260810102652.758719-1-sascha.bischoff@arm.com/
[2] https://sashiko.dev/#/patchset/20260724104819.1296803-1-sascha.bischoff%40arm.com
[3] https://lore.kernel.org/all/20260724104819.1296803-1-sascha.bischoff@arm.com/

Sascha Bischoff (4):
  KVM: arm64: vgic: Free gic_kvm_info on initialization failure
  KVM: arm64: vgic: Prevent speculative SPI array underflow
  KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs
  KVM: arm64: Validate GICv5 timer PPIs before claiming ownership

 arch/arm64/kvm/arch_timer.c     | 5 +++--
 arch/arm64/kvm/vgic/vgic-init.c | 4 +++-
 arch/arm64/kvm/vgic/vgic.c      | 7 +++++--
 include/kvm/arm_vgic.h          | 2 ++
 4 files changed, 13 insertions(+), 5 deletions(-)

-- 
2.34.1

             reply	other threads:[~2026-08-11 15:10 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-08-11 15:09 Sascha Bischoff [this message]
2026-08-11 15:10 ` [PATCH v2 1/4] KVM: arm64: vgic: Free gic_kvm_info on initialization failure Sascha Bischoff
2026-08-11 15:10 ` [PATCH v2 2/4] KVM: arm64: vgic: Prevent speculative SPI array underflow Sascha Bischoff
2026-08-11 15:11 ` [PATCH v2 3/4] KVM: arm64: vgic: Reject out-of-range GICv5 PPI IDs Sascha Bischoff
2026-08-11 15:11 ` [PATCH v2 4/4] KVM: arm64: Validate GICv5 timer PPIs before claiming ownership Sascha Bischoff

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